1 # SPDX-License-Identifier: GPL-2.0
5 select ARCH_32BIT_OFF_T
6 select ARCH_CLOCKSOURCE_DATA
7 select ARCH_DISCARD_MEMBLOCK if !HAVE_ARCH_PFN_VALID && !KEXEC
8 select ARCH_HAS_DEBUG_VIRTUAL if MMU
9 select ARCH_HAS_DEVMEM_IS_ALLOWED
10 select ARCH_HAS_ELF_RANDOMIZE
11 select ARCH_HAS_FORTIFY_SOURCE
13 select ARCH_HAS_MEMBARRIER_SYNC_CORE
14 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE
15 select ARCH_HAS_PHYS_TO_DMA
16 select ARCH_HAS_SETUP_DMA_OPS
17 select ARCH_HAS_SET_MEMORY
18 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
19 select ARCH_HAS_STRICT_MODULE_RWX if MMU
20 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU
21 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
22 select ARCH_HAVE_CUSTOM_GPIO_H
23 select ARCH_HAS_GCOV_PROFILE_ALL
24 select ARCH_MIGHT_HAVE_PC_PARPORT
25 select ARCH_NO_SG_CHAIN if !ARM_HAS_SG_CHAIN
26 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
27 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7
28 select ARCH_SUPPORTS_ATOMIC_RMW
29 select ARCH_USE_BUILTIN_BSWAP
30 select ARCH_USE_CMPXCHG_LOCKREF
31 select ARCH_WANT_IPC_PARSE_VERSION
32 select BUILDTIME_EXTABLE_SORT if MMU
33 select CLONE_BACKWARDS
34 select CPU_PM if SUSPEND || CPU_IDLE
35 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
36 select DMA_DECLARE_COHERENT
37 select DMA_REMAP if MMU
39 select EDAC_ATOMIC_SCRUB
40 select GENERIC_ALLOCATOR
41 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY
42 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI
43 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
44 select GENERIC_CPU_AUTOPROBE
45 select GENERIC_EARLY_IOREMAP
46 select GENERIC_IDLE_POLL_SETUP
47 select GENERIC_IRQ_PROBE
48 select GENERIC_IRQ_SHOW
49 select GENERIC_IRQ_SHOW_LEVEL
50 select GENERIC_PCI_IOMAP
51 select GENERIC_SCHED_CLOCK
52 select GENERIC_SMP_IDLE_THREAD
53 select GENERIC_STRNCPY_FROM_USER
54 select GENERIC_STRNLEN_USER
55 select HANDLE_DOMAIN_IRQ
56 select HARDIRQS_SW_RESEND
57 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT
58 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
59 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
60 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
61 select HAVE_ARCH_MMAP_RND_BITS if MMU
62 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT
63 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
64 select HAVE_ARCH_TRACEHOOK
65 select HAVE_ARM_SMCCC if CPU_V7
66 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32
67 select HAVE_CONTEXT_TRACKING
68 select HAVE_C_RECORDMCOUNT
69 select HAVE_DEBUG_KMEMLEAK
70 select HAVE_DMA_CONTIGUOUS if MMU
71 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
72 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE
73 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
74 select HAVE_EXIT_THREAD
75 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL
76 select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL && !CC_IS_CLANG
77 select HAVE_FUNCTION_TRACER if !XIP_KERNEL
78 select HAVE_GCC_PLUGINS
79 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)
80 select HAVE_IDE if PCI || ISA || PCMCIA
81 select HAVE_IRQ_TIME_ACCOUNTING
82 select HAVE_KERNEL_GZIP
83 select HAVE_KERNEL_LZ4
84 select HAVE_KERNEL_LZMA
85 select HAVE_KERNEL_LZO
87 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
88 select HAVE_KRETPROBES if HAVE_KPROBES
89 select HAVE_MOD_ARCH_SPECIFIC
91 select HAVE_OPROFILE if HAVE_PERF_EVENTS
92 select HAVE_OPTPROBES if !THUMB2_KERNEL
93 select HAVE_PERF_EVENTS
95 select HAVE_PERF_USER_STACK_DUMP
96 select HAVE_RCU_TABLE_FREE if SMP && ARM_LPAE
97 select HAVE_REGS_AND_STACK_ACCESS_API
99 select HAVE_STACKPROTECTOR
100 select HAVE_SYSCALL_TRACEPOINTS
102 select HAVE_VIRT_CPU_ACCOUNTING_GEN
103 select IRQ_FORCED_THREADING
104 select MODULES_USE_ELF_REL
105 select NEED_DMA_MAP_STATE
106 select OF_EARLY_FLATTREE if OF
108 select OLD_SIGSUSPEND3
109 select PCI_SYSCALL if PCI
110 select PERF_USE_VMALLOC
113 select SYS_SUPPORTS_APM_EMULATION
114 # Above selects are sorted alphabetically; please add new ones
115 # according to that. Thanks.
117 The ARM series is a line of low-power-consumption RISC chip designs
118 licensed by ARM Ltd and targeted at embedded applications and
119 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
120 manufactured, but legacy ARM-based PC hardware remains popular in
121 Europe. There is an ARM Linux project with a web page at
122 <http://www.arm.linux.org.uk/>.
124 config ARM_HAS_SG_CHAIN
127 config ARM_DMA_USE_IOMMU
129 select ARM_HAS_SG_CHAIN
130 select NEED_SG_DMA_LENGTH
134 config ARM_DMA_IOMMU_ALIGNMENT
135 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
139 DMA mapping framework by default aligns all buffers to the smallest
140 PAGE_SIZE order which is greater than or equal to the requested buffer
141 size. This works well for buffers up to a few hundreds kilobytes, but
142 for larger buffers it just a waste of address space. Drivers which has
143 relatively small addressing window (like 64Mib) might run out of
144 virtual space with just a few allocations.
146 With this parameter you can specify the maximum PAGE_SIZE order for
147 DMA IOMMU buffers. Larger buffers will be aligned only to this
148 specified order. The order is expressed as a power of two multiplied
153 config SYS_SUPPORTS_APM_EMULATION
158 select GENERIC_ALLOCATOR
169 config STACKTRACE_SUPPORT
173 config LOCKDEP_SUPPORT
177 config TRACE_IRQFLAGS_SUPPORT
181 config ARCH_HAS_ILOG2_U32
184 config ARCH_HAS_ILOG2_U64
187 config ARCH_HAS_BANDGAP
190 config FIX_EARLYCON_MEM
193 config GENERIC_HWEIGHT
197 config GENERIC_CALIBRATE_DELAY
201 config ARCH_MAY_HAVE_PC_FDC
207 config ARCH_SUPPORTS_UPROBES
210 config ARCH_HAS_DMA_SET_COHERENT_MASK
213 config GENERIC_ISA_DMA
219 config NEED_RET_TO_USER
225 config ARM_PATCH_PHYS_VIRT
226 bool "Patch physical to virtual translations at runtime" if EMBEDDED
228 depends on !XIP_KERNEL && MMU
230 Patch phys-to-virt and virt-to-phys translation functions at
231 boot and module load time according to the position of the
232 kernel in system memory.
234 This can only be used with non-XIP MMU kernels where the base
235 of physical memory is at a 16MB boundary.
237 Only disable this option if you know that you do not require
238 this feature (eg, building a kernel for a single machine) and
239 you need to shrink the kernel to the minimal size.
241 config NEED_MACH_IO_H
244 Select this when mach/io.h is required to provide special
245 definitions for this platform. The need for mach/io.h should
246 be avoided when possible.
248 config NEED_MACH_MEMORY_H
251 Select this when mach/memory.h is required to provide special
252 definitions for this platform. The need for mach/memory.h should
253 be avoided when possible.
256 hex "Physical address of main memory" if MMU
257 depends on !ARM_PATCH_PHYS_VIRT
258 default DRAM_BASE if !MMU
259 default 0x00000000 if ARCH_EBSA110 || \
265 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
266 default 0x20000000 if ARCH_S5PV210
267 default 0xc0000000 if ARCH_SA1100
269 Please provide the physical address corresponding to the
270 location of main memory in your system.
276 config PGTABLE_LEVELS
278 default 3 if ARM_LPAE
284 bool "MMU-based Paged Memory Management Support"
287 Select if you want MMU-based virtualised addressing space
288 support by paged memory management. If unsure, say 'Y'.
290 config ARCH_MMAP_RND_BITS_MIN
293 config ARCH_MMAP_RND_BITS_MAX
294 default 14 if PAGE_OFFSET=0x40000000
295 default 15 if PAGE_OFFSET=0x80000000
299 # The "ARM system type" choice list is ordered alphabetically by option
300 # text. Please add new entries in the option alphabetic order.
303 prompt "ARM system type"
304 default ARM_SINGLE_ARMV7M if !MMU
305 default ARCH_MULTIPLATFORM if MMU
307 config ARCH_MULTIPLATFORM
308 bool "Allow multiple platforms to be selected"
310 select ARM_HAS_SG_CHAIN
311 select ARM_PATCH_PHYS_VIRT
315 select GENERIC_CLOCKEVENTS
316 select GENERIC_IRQ_MULTI_HANDLER
318 select PCI_DOMAINS_GENERIC if PCI
322 config ARM_SINGLE_ARMV7M
323 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
330 select GENERIC_CLOCKEVENTS
337 select ARCH_USES_GETTIMEOFFSET
340 select NEED_MACH_IO_H
341 select NEED_MACH_MEMORY_H
344 This is an evaluation board for the StrongARM processor available
345 from Digital. It has limited hardware on-board, including an
346 Ethernet interface, two PCMCIA sockets, two serial ports and a
351 select ARCH_SPARSEMEM_ENABLE
353 imply ARM_PATCH_PHYS_VIRT
359 select GENERIC_CLOCKEVENTS
362 This enables support for the Cirrus EP93xx series of CPUs.
364 config ARCH_FOOTBRIDGE
368 select GENERIC_CLOCKEVENTS
370 select NEED_MACH_IO_H if !MMU
371 select NEED_MACH_MEMORY_H
373 Support for systems based on the DC21285 companion chip
374 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
377 bool "Hilscher NetX based"
381 select GENERIC_CLOCKEVENTS
383 This enables support for systems based on the Hilscher NetX Soc
389 select NEED_MACH_MEMORY_H
390 select NEED_RET_TO_USER
396 Support for Intel's IOP13XX (XScale) family of processors.
404 select NEED_RET_TO_USER
408 Support for Intel's 80219 and IOP32X (XScale) family of
417 select NEED_RET_TO_USER
421 Support for Intel's IOP33X (XScale) family of processors.
426 select ARCH_HAS_DMA_SET_COHERENT_MASK
427 select ARCH_SUPPORTS_BIG_ENDIAN
430 select DMABOUNCE if PCI
431 select GENERIC_CLOCKEVENTS
434 select NEED_MACH_IO_H
435 select USB_EHCI_BIG_ENDIAN_DESC
436 select USB_EHCI_BIG_ENDIAN_MMIO
438 Support for Intel's IXP4XX (XScale) family of processors.
443 select GENERIC_CLOCKEVENTS
444 select GENERIC_IRQ_MULTI_HANDLER
450 select PLAT_ORION_LEGACY
452 select PM_GENERIC_DOMAINS if PM
454 Support for the Marvell Dove SoC 88AP510
457 bool "Micrel/Kendin KS8695"
460 select GENERIC_CLOCKEVENTS
462 select NEED_MACH_MEMORY_H
464 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
465 System-on-Chip devices.
468 bool "Nuvoton W90X900 CPU"
472 select GENERIC_CLOCKEVENTS
475 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
476 At present, the w90x900 has been renamed nuc900, regarding
477 the ARM series product line, you can login the following
478 link address to know more.
480 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
481 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
487 select CLKSRC_LPC32XX
490 select GENERIC_CLOCKEVENTS
491 select GENERIC_IRQ_MULTI_HANDLER
496 Support for the NXP LPC32XX family of processors
499 bool "PXA2xx/PXA3xx-based"
502 select ARM_CPU_SUSPEND if PM
509 select CPU_XSCALE if !CPU_XSC3
510 select GENERIC_CLOCKEVENTS
511 select GENERIC_IRQ_MULTI_HANDLER
519 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
525 select ARCH_MAY_HAVE_PC_FDC
526 select ARCH_SPARSEMEM_ENABLE
527 select ARCH_USES_GETTIMEOFFSET
531 select HAVE_PATA_PLATFORM
533 select NEED_MACH_IO_H
534 select NEED_MACH_MEMORY_H
537 On the Acorn Risc-PC, Linux can support the internal IDE disk and
538 CD-ROM interface, serial and parallel port, and the floppy drive.
543 select ARCH_SPARSEMEM_ENABLE
547 select TIMER_OF if OF
550 select GENERIC_CLOCKEVENTS
551 select GENERIC_IRQ_MULTI_HANDLER
556 select NEED_MACH_MEMORY_H
559 Support for StrongARM 11x0 based boards.
562 bool "Samsung S3C24XX SoCs"
565 select CLKSRC_SAMSUNG_PWM
566 select GENERIC_CLOCKEVENTS
569 select GENERIC_IRQ_MULTI_HANDLER
570 select HAVE_S3C2410_I2C if I2C
571 select HAVE_S3C2410_WATCHDOG if WATCHDOG
572 select HAVE_S3C_RTC if RTC_CLASS
573 select NEED_MACH_IO_H
577 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
578 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
579 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
580 Samsung SMDK2410 development board (and derivatives).
584 select ARCH_HAS_HOLES_MEMORYMODEL
587 select GENERIC_ALLOCATOR
588 select GENERIC_CLOCKEVENTS
589 select GENERIC_IRQ_CHIP
590 select GENERIC_IRQ_MULTI_HANDLER
593 select PM_GENERIC_DOMAINS if PM
594 select PM_GENERIC_DOMAINS_OF if PM && OF
596 select RESET_CONTROLLER
601 Support for TI's DaVinci platform.
606 select ARCH_HAS_HOLES_MEMORYMODEL
610 select GENERIC_CLOCKEVENTS
611 select GENERIC_IRQ_CHIP
612 select GENERIC_IRQ_MULTI_HANDLER
616 select NEED_MACH_IO_H if PCCARD
617 select NEED_MACH_MEMORY_H
620 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
624 menu "Multiple platform selection"
625 depends on ARCH_MULTIPLATFORM
627 comment "CPU Core family selection"
630 bool "ARMv4 based platforms (FA526)"
631 depends on !ARCH_MULTI_V6_V7
632 select ARCH_MULTI_V4_V5
635 config ARCH_MULTI_V4T
636 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
637 depends on !ARCH_MULTI_V6_V7
638 select ARCH_MULTI_V4_V5
639 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
640 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
641 CPU_ARM925T || CPU_ARM940T)
644 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
645 depends on !ARCH_MULTI_V6_V7
646 select ARCH_MULTI_V4_V5
647 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
648 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
649 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
651 config ARCH_MULTI_V4_V5
655 bool "ARMv6 based platforms (ARM11)"
656 select ARCH_MULTI_V6_V7
660 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
662 select ARCH_MULTI_V6_V7
666 config ARCH_MULTI_V6_V7
668 select MIGHT_HAVE_CACHE_L2X0
670 config ARCH_MULTI_CPU_AUTO
671 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
677 bool "Dummy Virtual Machine"
678 depends on ARCH_MULTI_V7
681 select ARM_GIC_V2M if PCI
683 select ARM_GIC_V3_ITS if PCI
685 select HAVE_ARM_ARCH_TIMER
686 select ARCH_SUPPORTS_BIG_ENDIAN
689 # This is sorted alphabetically by mach-* pathname. However, plat-*
690 # Kconfigs may be included either alphabetically (according to the
691 # plat- suffix) or along side the corresponding mach-* source.
693 source "arch/arm/mach-actions/Kconfig"
695 source "arch/arm/mach-alpine/Kconfig"
697 source "arch/arm/mach-artpec/Kconfig"
699 source "arch/arm/mach-asm9260/Kconfig"
701 source "arch/arm/mach-aspeed/Kconfig"
703 source "arch/arm/mach-at91/Kconfig"
705 source "arch/arm/mach-axxia/Kconfig"
707 source "arch/arm/mach-bcm/Kconfig"
709 source "arch/arm/mach-berlin/Kconfig"
711 source "arch/arm/mach-clps711x/Kconfig"
713 source "arch/arm/mach-cns3xxx/Kconfig"
715 source "arch/arm/mach-davinci/Kconfig"
717 source "arch/arm/mach-digicolor/Kconfig"
719 source "arch/arm/mach-dove/Kconfig"
721 source "arch/arm/mach-ep93xx/Kconfig"
723 source "arch/arm/mach-exynos/Kconfig"
724 source "arch/arm/plat-samsung/Kconfig"
726 source "arch/arm/mach-footbridge/Kconfig"
728 source "arch/arm/mach-gemini/Kconfig"
730 source "arch/arm/mach-highbank/Kconfig"
732 source "arch/arm/mach-hisi/Kconfig"
734 source "arch/arm/mach-imx/Kconfig"
736 source "arch/arm/mach-integrator/Kconfig"
738 source "arch/arm/mach-iop13xx/Kconfig"
740 source "arch/arm/mach-iop32x/Kconfig"
742 source "arch/arm/mach-iop33x/Kconfig"
744 source "arch/arm/mach-ixp4xx/Kconfig"
746 source "arch/arm/mach-keystone/Kconfig"
748 source "arch/arm/mach-ks8695/Kconfig"
750 source "arch/arm/mach-mediatek/Kconfig"
752 source "arch/arm/mach-meson/Kconfig"
754 source "arch/arm/mach-milbeaut/Kconfig"
756 source "arch/arm/mach-mmp/Kconfig"
758 source "arch/arm/mach-moxart/Kconfig"
760 source "arch/arm/mach-mv78xx0/Kconfig"
762 source "arch/arm/mach-mvebu/Kconfig"
764 source "arch/arm/mach-mxs/Kconfig"
766 source "arch/arm/mach-netx/Kconfig"
768 source "arch/arm/mach-nomadik/Kconfig"
770 source "arch/arm/mach-npcm/Kconfig"
772 source "arch/arm/mach-nspire/Kconfig"
774 source "arch/arm/plat-omap/Kconfig"
776 source "arch/arm/mach-omap1/Kconfig"
778 source "arch/arm/mach-omap2/Kconfig"
780 source "arch/arm/mach-orion5x/Kconfig"
782 source "arch/arm/mach-oxnas/Kconfig"
784 source "arch/arm/mach-picoxcell/Kconfig"
786 source "arch/arm/mach-prima2/Kconfig"
788 source "arch/arm/mach-pxa/Kconfig"
789 source "arch/arm/plat-pxa/Kconfig"
791 source "arch/arm/mach-qcom/Kconfig"
793 source "arch/arm/mach-rda/Kconfig"
795 source "arch/arm/mach-realview/Kconfig"
797 source "arch/arm/mach-rockchip/Kconfig"
799 source "arch/arm/mach-s3c24xx/Kconfig"
801 source "arch/arm/mach-s3c64xx/Kconfig"
803 source "arch/arm/mach-s5pv210/Kconfig"
805 source "arch/arm/mach-sa1100/Kconfig"
807 source "arch/arm/mach-shmobile/Kconfig"
809 source "arch/arm/mach-socfpga/Kconfig"
811 source "arch/arm/mach-spear/Kconfig"
813 source "arch/arm/mach-sti/Kconfig"
815 source "arch/arm/mach-stm32/Kconfig"
817 source "arch/arm/mach-sunxi/Kconfig"
819 source "arch/arm/mach-tango/Kconfig"
821 source "arch/arm/mach-tegra/Kconfig"
823 source "arch/arm/mach-u300/Kconfig"
825 source "arch/arm/mach-uniphier/Kconfig"
827 source "arch/arm/mach-ux500/Kconfig"
829 source "arch/arm/mach-versatile/Kconfig"
831 source "arch/arm/mach-vexpress/Kconfig"
832 source "arch/arm/plat-versatile/Kconfig"
834 source "arch/arm/mach-vt8500/Kconfig"
836 source "arch/arm/mach-w90x900/Kconfig"
838 source "arch/arm/mach-zx/Kconfig"
840 source "arch/arm/mach-zynq/Kconfig"
842 # ARMv7-M architecture
844 bool "Energy Micro efm32"
845 depends on ARM_SINGLE_ARMV7M
848 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
852 bool "NXP LPC18xx/LPC43xx"
853 depends on ARM_SINGLE_ARMV7M
854 select ARCH_HAS_RESET_CONTROLLER
856 select CLKSRC_LPC32XX
859 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
860 high performance microcontrollers.
863 bool "ARM MPS2 platform"
864 depends on ARM_SINGLE_ARMV7M
868 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
869 with a range of available cores like Cortex-M3/M4/M7.
871 Please, note that depends which Application Note is used memory map
872 for the platform may vary, so adjustment of RAM base might be needed.
874 # Definitions to make life easier
880 select GENERIC_CLOCKEVENTS
886 select GENERIC_IRQ_CHIP
889 config PLAT_ORION_LEGACY
896 config PLAT_VERSATILE
899 source "arch/arm/firmware/Kconfig"
901 source "arch/arm/mm/Kconfig"
904 bool "Enable iWMMXt support"
905 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
906 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
908 Enable support for iWMMXt context switching at run time if
909 running on a CPU that supports it.
912 source "arch/arm/Kconfig-nommu"
915 config PJ4B_ERRATA_4742
916 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
917 depends on CPU_PJ4B && MACH_ARMADA_370
920 When coming out of either a Wait for Interrupt (WFI) or a Wait for
921 Event (WFE) IDLE states, a specific timing sensitivity exists between
922 the retiring WFI/WFE instructions and the newly issued subsequent
923 instructions. This sensitivity can result in a CPU hang scenario.
925 The software must insert either a Data Synchronization Barrier (DSB)
926 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
929 config ARM_ERRATA_326103
930 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
933 Executing a SWP instruction to read-only memory does not set bit 11
934 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
935 treat the access as a read, preventing a COW from occurring and
936 causing the faulting task to livelock.
938 config ARM_ERRATA_411920
939 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
940 depends on CPU_V6 || CPU_V6K
942 Invalidation of the Instruction Cache operation can
943 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
944 It does not affect the MPCore. This option enables the ARM Ltd.
945 recommended workaround.
947 config ARM_ERRATA_430973
948 bool "ARM errata: Stale prediction on replaced interworking branch"
951 This option enables the workaround for the 430973 Cortex-A8
952 r1p* erratum. If a code sequence containing an ARM/Thumb
953 interworking branch is replaced with another code sequence at the
954 same virtual address, whether due to self-modifying code or virtual
955 to physical address re-mapping, Cortex-A8 does not recover from the
956 stale interworking branch prediction. This results in Cortex-A8
957 executing the new code sequence in the incorrect ARM or Thumb state.
958 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
959 and also flushes the branch target cache at every context switch.
960 Note that setting specific bits in the ACTLR register may not be
961 available in non-secure mode.
963 config ARM_ERRATA_458693
964 bool "ARM errata: Processor deadlock when a false hazard is created"
966 depends on !ARCH_MULTIPLATFORM
968 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
969 erratum. For very specific sequences of memory operations, it is
970 possible for a hazard condition intended for a cache line to instead
971 be incorrectly associated with a different cache line. This false
972 hazard might then cause a processor deadlock. The workaround enables
973 the L1 caching of the NEON accesses and disables the PLD instruction
974 in the ACTLR register. Note that setting specific bits in the ACTLR
975 register may not be available in non-secure mode.
977 config ARM_ERRATA_460075
978 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
980 depends on !ARCH_MULTIPLATFORM
982 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
983 erratum. Any asynchronous access to the L2 cache may encounter a
984 situation in which recent store transactions to the L2 cache are lost
985 and overwritten with stale memory contents from external memory. The
986 workaround disables the write-allocate mode for the L2 cache via the
987 ACTLR register. Note that setting specific bits in the ACTLR register
988 may not be available in non-secure mode.
990 config ARM_ERRATA_742230
991 bool "ARM errata: DMB operation may be faulty"
992 depends on CPU_V7 && SMP
993 depends on !ARCH_MULTIPLATFORM
995 This option enables the workaround for the 742230 Cortex-A9
996 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
997 between two write operations may not ensure the correct visibility
998 ordering of the two writes. This workaround sets a specific bit in
999 the diagnostic register of the Cortex-A9 which causes the DMB
1000 instruction to behave as a DSB, ensuring the correct behaviour of
1003 config ARM_ERRATA_742231
1004 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1005 depends on CPU_V7 && SMP
1006 depends on !ARCH_MULTIPLATFORM
1008 This option enables the workaround for the 742231 Cortex-A9
1009 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1010 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1011 accessing some data located in the same cache line, may get corrupted
1012 data due to bad handling of the address hazard when the line gets
1013 replaced from one of the CPUs at the same time as another CPU is
1014 accessing it. This workaround sets specific bits in the diagnostic
1015 register of the Cortex-A9 which reduces the linefill issuing
1016 capabilities of the processor.
1018 config ARM_ERRATA_643719
1019 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1020 depends on CPU_V7 && SMP
1023 This option enables the workaround for the 643719 Cortex-A9 (prior to
1024 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1025 register returns zero when it should return one. The workaround
1026 corrects this value, ensuring cache maintenance operations which use
1027 it behave as intended and avoiding data corruption.
1029 config ARM_ERRATA_720789
1030 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1033 This option enables the workaround for the 720789 Cortex-A9 (prior to
1034 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1035 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1036 As a consequence of this erratum, some TLB entries which should be
1037 invalidated are not, resulting in an incoherency in the system page
1038 tables. The workaround changes the TLB flushing routines to invalidate
1039 entries regardless of the ASID.
1041 config ARM_ERRATA_743622
1042 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1044 depends on !ARCH_MULTIPLATFORM
1046 This option enables the workaround for the 743622 Cortex-A9
1047 (r2p*) erratum. Under very rare conditions, a faulty
1048 optimisation in the Cortex-A9 Store Buffer may lead to data
1049 corruption. This workaround sets a specific bit in the diagnostic
1050 register of the Cortex-A9 which disables the Store Buffer
1051 optimisation, preventing the defect from occurring. This has no
1052 visible impact on the overall performance or power consumption of the
1055 config ARM_ERRATA_751472
1056 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1058 depends on !ARCH_MULTIPLATFORM
1060 This option enables the workaround for the 751472 Cortex-A9 (prior
1061 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1062 completion of a following broadcasted operation if the second
1063 operation is received by a CPU before the ICIALLUIS has completed,
1064 potentially leading to corrupted entries in the cache or TLB.
1066 config ARM_ERRATA_754322
1067 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1070 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1071 r3p*) erratum. A speculative memory access may cause a page table walk
1072 which starts prior to an ASID switch but completes afterwards. This
1073 can populate the micro-TLB with a stale entry which may be hit with
1074 the new ASID. This workaround places two dsb instructions in the mm
1075 switching code so that no page table walks can cross the ASID switch.
1077 config ARM_ERRATA_754327
1078 bool "ARM errata: no automatic Store Buffer drain"
1079 depends on CPU_V7 && SMP
1081 This option enables the workaround for the 754327 Cortex-A9 (prior to
1082 r2p0) erratum. The Store Buffer does not have any automatic draining
1083 mechanism and therefore a livelock may occur if an external agent
1084 continuously polls a memory location waiting to observe an update.
1085 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1086 written polling loops from denying visibility of updates to memory.
1088 config ARM_ERRATA_364296
1089 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1092 This options enables the workaround for the 364296 ARM1136
1093 r0p2 erratum (possible cache data corruption with
1094 hit-under-miss enabled). It sets the undocumented bit 31 in
1095 the auxiliary control register and the FI bit in the control
1096 register, thus disabling hit-under-miss without putting the
1097 processor into full low interrupt latency mode. ARM11MPCore
1100 config ARM_ERRATA_764369
1101 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1102 depends on CPU_V7 && SMP
1104 This option enables the workaround for erratum 764369
1105 affecting Cortex-A9 MPCore with two or more processors (all
1106 current revisions). Under certain timing circumstances, a data
1107 cache line maintenance operation by MVA targeting an Inner
1108 Shareable memory region may fail to proceed up to either the
1109 Point of Coherency or to the Point of Unification of the
1110 system. This workaround adds a DSB instruction before the
1111 relevant cache maintenance functions and sets a specific bit
1112 in the diagnostic control register of the SCU.
1114 config ARM_ERRATA_775420
1115 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1118 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1119 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1120 operation aborts with MMU exception, it might cause the processor
1121 to deadlock. This workaround puts DSB before executing ISB if
1122 an abort may occur on cache maintenance.
1124 config ARM_ERRATA_798181
1125 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1126 depends on CPU_V7 && SMP
1128 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1129 adequately shooting down all use of the old entries. This
1130 option enables the Linux kernel workaround for this erratum
1131 which sends an IPI to the CPUs that are running the same ASID
1132 as the one being invalidated.
1134 config ARM_ERRATA_773022
1135 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1138 This option enables the workaround for the 773022 Cortex-A15
1139 (up to r0p4) erratum. In certain rare sequences of code, the
1140 loop buffer may deliver incorrect instructions. This
1141 workaround disables the loop buffer to avoid the erratum.
1143 config ARM_ERRATA_818325_852422
1144 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption"
1147 This option enables the workaround for:
1148 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
1149 instruction might deadlock. Fixed in r0p1.
1150 - Cortex-A12 852422: Execution of a sequence of instructions might
1151 lead to either a data corruption or a CPU deadlock. Not fixed in
1152 any Cortex-A12 cores yet.
1153 This workaround for all both errata involves setting bit[12] of the
1154 Feature Register. This bit disables an optimisation applied to a
1155 sequence of 2 instructions that use opposing condition codes.
1157 config ARM_ERRATA_821420
1158 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
1161 This option enables the workaround for the 821420 Cortex-A12
1162 (all revs) erratum. In very rare timing conditions, a sequence
1163 of VMOV to Core registers instructions, for which the second
1164 one is in the shadow of a branch or abort, can lead to a
1165 deadlock when the VMOV instructions are issued out-of-order.
1167 config ARM_ERRATA_825619
1168 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"
1171 This option enables the workaround for the 825619 Cortex-A12
1172 (all revs) erratum. Within rare timing constraints, executing a
1173 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable
1174 and Device/Strongly-Ordered loads and stores might cause deadlock
1176 config ARM_ERRATA_852421
1177 bool "ARM errata: A17: DMB ST might fail to create order between stores"
1180 This option enables the workaround for the 852421 Cortex-A17
1181 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions,
1182 execution of a DMB ST instruction might fail to properly order
1183 stores from GroupA and stores from GroupB.
1185 config ARM_ERRATA_852423
1186 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
1189 This option enables the workaround for:
1190 - Cortex-A17 852423: Execution of a sequence of instructions might
1191 lead to either a data corruption or a CPU deadlock. Not fixed in
1192 any Cortex-A17 cores yet.
1193 This is identical to Cortex-A12 erratum 852422. It is a separate
1194 config option from the A12 erratum due to the way errata are checked
1199 source "arch/arm/common/Kconfig"
1206 Find out whether you have ISA slots on your motherboard. ISA is the
1207 name of a bus system, i.e. the way the CPU talks to the other stuff
1208 inside your box. Other bus systems are PCI, EISA, MicroChannel
1209 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1210 newer boards don't support it. If you have ISA, say Y, otherwise N.
1212 # Select ISA DMA controller support
1217 # Select ISA DMA interface
1221 config PCI_NANOENGINE
1222 bool "BSE nanoEngine PCI support"
1223 depends on SA1100_NANOENGINE
1225 Enable PCI on the BSE nanoEngine board.
1227 config PCI_HOST_ITE8152
1229 depends on PCI && MACH_ARMCORE
1235 menu "Kernel Features"
1240 This option should be selected by machines which have an SMP-
1243 The only effect of this option is to make the SMP-related
1244 options available to the user for configuration.
1247 bool "Symmetric Multi-Processing"
1248 depends on CPU_V6K || CPU_V7
1249 depends on GENERIC_CLOCKEVENTS
1251 depends on MMU || ARM_MPU
1254 This enables support for systems with more than one CPU. If you have
1255 a system with only one CPU, say N. If you have a system with more
1256 than one CPU, say Y.
1258 If you say N here, the kernel will run on uni- and multiprocessor
1259 machines, but will use only one CPU of a multiprocessor machine. If
1260 you say Y here, the kernel will run on many, but not all,
1261 uniprocessor machines. On a uniprocessor machine, the kernel
1262 will run faster if you say N here.
1264 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1265 <file:Documentation/lockup-watchdogs.txt> and the SMP-HOWTO available at
1266 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1268 If you don't know what to do here, say N.
1271 bool "Allow booting SMP kernel on uniprocessor systems"
1272 depends on SMP && !XIP_KERNEL && MMU
1275 SMP kernels contain instructions which fail on non-SMP processors.
1276 Enabling this option allows the kernel to modify itself to make
1277 these instructions safe. Disabling it allows about 1K of space
1280 If you don't know what to do here, say Y.
1282 config ARM_CPU_TOPOLOGY
1283 bool "Support cpu topology definition"
1284 depends on SMP && CPU_V7
1287 Support ARM cpu topology definition. The MPIDR register defines
1288 affinity between processors which is then used to describe the cpu
1289 topology of an ARM System.
1292 bool "Multi-core scheduler support"
1293 depends on ARM_CPU_TOPOLOGY
1295 Multi-core scheduler support improves the CPU scheduler's decision
1296 making when dealing with multi-core CPU chips at a cost of slightly
1297 increased overhead in some places. If unsure say N here.
1300 bool "SMT scheduler support"
1301 depends on ARM_CPU_TOPOLOGY
1303 Improves the CPU scheduler's decision making when dealing with
1304 MultiThreading at a cost of slightly increased overhead in some
1305 places. If unsure say N here.
1310 This option enables support for the ARM snoop control unit
1312 config HAVE_ARM_ARCH_TIMER
1313 bool "Architected timer support"
1315 select ARM_ARCH_TIMER
1316 select GENERIC_CLOCKEVENTS
1318 This option enables support for the ARM architected timer
1323 This options enables support for the ARM timer and watchdog unit
1326 bool "Multi-Cluster Power Management"
1327 depends on CPU_V7 && SMP
1329 This option provides the common power management infrastructure
1330 for (multi-)cluster based systems, such as big.LITTLE based
1333 config MCPM_QUAD_CLUSTER
1337 To avoid wasting resources unnecessarily, MCPM only supports up
1338 to 2 clusters by default.
1339 Platforms with 3 or 4 clusters that use MCPM must select this
1340 option to allow the additional clusters to be managed.
1343 bool "big.LITTLE support (Experimental)"
1344 depends on CPU_V7 && SMP
1347 This option enables support selections for the big.LITTLE
1348 system architecture.
1351 bool "big.LITTLE switcher support"
1352 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1355 The big.LITTLE "switcher" provides the core functionality to
1356 transparently handle transition between a cluster of A15's
1357 and a cluster of A7's in a big.LITTLE system.
1359 config BL_SWITCHER_DUMMY_IF
1360 tristate "Simple big.LITTLE switcher user interface"
1361 depends on BL_SWITCHER && DEBUG_KERNEL
1363 This is a simple and dummy char dev interface to control
1364 the big.LITTLE switcher core code. It is meant for
1365 debugging purposes only.
1368 prompt "Memory split"
1372 Select the desired split between kernel and user memory.
1374 If you are not absolutely sure what you are doing, leave this
1378 bool "3G/1G user/kernel split"
1379 config VMSPLIT_3G_OPT
1380 depends on !ARM_LPAE
1381 bool "3G/1G user/kernel split (for full 1G low memory)"
1383 bool "2G/2G user/kernel split"
1385 bool "1G/3G user/kernel split"
1390 default PHYS_OFFSET if !MMU
1391 default 0x40000000 if VMSPLIT_1G
1392 default 0x80000000 if VMSPLIT_2G
1393 default 0xB0000000 if VMSPLIT_3G_OPT
1397 int "Maximum number of CPUs (2-32)"
1403 bool "Support for hot-pluggable CPUs"
1405 select GENERIC_IRQ_MIGRATION
1407 Say Y here to experiment with turning CPUs off and on. CPUs
1408 can be controlled through /sys/devices/system/cpu.
1411 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1412 depends on HAVE_ARM_SMCCC
1415 Say Y here if you want Linux to communicate with system firmware
1416 implementing the PSCI specification for CPU-centric power
1417 management operations described in ARM document number ARM DEN
1418 0022A ("Power State Coordination Interface System Software on
1421 # The GPIO number here must be sorted by descending number. In case of
1422 # a multiplatform kernel, we just want the highest value required by the
1423 # selected platforms.
1426 default 2048 if ARCH_SOCFPGA
1427 default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \
1429 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1430 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1431 default 416 if ARCH_SUNXI
1432 default 392 if ARCH_U8500
1433 default 352 if ARCH_VT8500
1434 default 288 if ARCH_ROCKCHIP
1435 default 264 if MACH_H4700
1438 Maximum number of GPIOs in the system.
1440 If unsure, leave the default value.
1444 default 200 if ARCH_EBSA110
1445 default 128 if SOC_AT91RM9200
1449 depends on HZ_FIXED = 0
1450 prompt "Timer frequency"
1474 default HZ_FIXED if HZ_FIXED != 0
1475 default 100 if HZ_100
1476 default 200 if HZ_200
1477 default 250 if HZ_250
1478 default 300 if HZ_300
1479 default 500 if HZ_500
1483 def_bool HIGH_RES_TIMERS
1485 config THUMB2_KERNEL
1486 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1487 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1488 default y if CPU_THUMBONLY
1491 By enabling this option, the kernel will be compiled in
1496 config THUMB2_AVOID_R_ARM_THM_JUMP11
1497 bool "Work around buggy Thumb-2 short branch relocations in gas"
1498 depends on THUMB2_KERNEL && MODULES
1501 Various binutils versions can resolve Thumb-2 branches to
1502 locally-defined, preemptible global symbols as short-range "b.n"
1503 branch instructions.
1505 This is a problem, because there's no guarantee the final
1506 destination of the symbol, or any candidate locations for a
1507 trampoline, are within range of the branch. For this reason, the
1508 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1509 relocation in modules at all, and it makes little sense to add
1512 The symptom is that the kernel fails with an "unsupported
1513 relocation" error when loading some modules.
1515 Until fixed tools are available, passing
1516 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1517 code which hits this problem, at the cost of a bit of extra runtime
1518 stack usage in some cases.
1520 The problem is described in more detail at:
1521 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1523 Only Thumb-2 kernels are affected.
1525 Unless you are sure your tools don't have this problem, say Y.
1527 config ARM_PATCH_IDIV
1528 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1529 depends on CPU_32v7 && !XIP_KERNEL
1532 The ARM compiler inserts calls to __aeabi_idiv() and
1533 __aeabi_uidiv() when it needs to perform division on signed
1534 and unsigned integers. Some v7 CPUs have support for the sdiv
1535 and udiv instructions that can be used to implement those
1538 Enabling this option allows the kernel to modify itself to
1539 replace the first two instructions of these library functions
1540 with the sdiv or udiv plus "bx lr" instructions when the CPU
1541 it is running on supports them. Typically this will be faster
1542 and less power intensive than running the original library
1543 code to do integer division.
1546 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && !CPU_V7M && !CPU_V6 && !CPU_V6K
1547 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K
1549 This option allows for the kernel to be compiled using the latest
1550 ARM ABI (aka EABI). This is only useful if you are using a user
1551 space environment that is also compiled with EABI.
1553 Since there are major incompatibilities between the legacy ABI and
1554 EABI, especially with regard to structure member alignment, this
1555 option also changes the kernel syscall calling convention to
1556 disambiguate both ABIs and allow for backward compatibility support
1557 (selected with CONFIG_OABI_COMPAT).
1559 To use this you need GCC version 4.0.0 or later.
1562 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1563 depends on AEABI && !THUMB2_KERNEL
1565 This option preserves the old syscall interface along with the
1566 new (ARM EABI) one. It also provides a compatibility layer to
1567 intercept syscalls that have structure arguments which layout
1568 in memory differs between the legacy ABI and the new ARM EABI
1569 (only for non "thumb" binaries). This option adds a tiny
1570 overhead to all syscalls and produces a slightly larger kernel.
1572 The seccomp filter system will not be available when this is
1573 selected, since there is no way yet to sensibly distinguish
1574 between calling conventions during filtering.
1576 If you know you'll be using only pure EABI user space then you
1577 can say N here. If this option is not selected and you attempt
1578 to execute a legacy ABI binary then the result will be
1579 UNPREDICTABLE (in fact it can be predicted that it won't work
1580 at all). If in doubt say N.
1582 config ARCH_HAS_HOLES_MEMORYMODEL
1585 config ARCH_SPARSEMEM_ENABLE
1588 config ARCH_SPARSEMEM_DEFAULT
1589 def_bool ARCH_SPARSEMEM_ENABLE
1591 config ARCH_SELECT_MEMORY_MODEL
1592 def_bool ARCH_SPARSEMEM_ENABLE
1594 config HAVE_ARCH_PFN_VALID
1595 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1597 config HAVE_GENERIC_GUP
1602 bool "High Memory Support"
1605 The address space of ARM processors is only 4 Gigabytes large
1606 and it has to accommodate user address space, kernel address
1607 space as well as some memory mapped IO. That means that, if you
1608 have a large amount of physical memory and/or IO, not all of the
1609 memory can be "permanently mapped" by the kernel. The physical
1610 memory that is not permanently mapped is called "high memory".
1612 Depending on the selected kernel/user memory split, minimum
1613 vmalloc space and actual amount of RAM, you may not need this
1614 option which should result in a slightly faster kernel.
1619 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1623 The VM uses one page of physical memory for each page table.
1624 For systems with a lot of processes, this can use a lot of
1625 precious low memory, eventually leading to low memory being
1626 consumed by page tables. Setting this option will allow
1627 user-space 2nd level page tables to reside in high memory.
1629 config CPU_SW_DOMAIN_PAN
1630 bool "Enable use of CPU domains to implement privileged no-access"
1631 depends on MMU && !ARM_LPAE
1634 Increase kernel security by ensuring that normal kernel accesses
1635 are unable to access userspace addresses. This can help prevent
1636 use-after-free bugs becoming an exploitable privilege escalation
1637 by ensuring that magic values (such as LIST_POISON) will always
1638 fault when dereferenced.
1640 CPUs with low-vector mappings use a best-efforts implementation.
1641 Their lower 1MB needs to remain accessible for the vectors, but
1642 the remainder of userspace will become appropriately inaccessible.
1644 config HW_PERF_EVENTS
1648 config SYS_SUPPORTS_HUGETLBFS
1652 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1656 config ARCH_WANT_GENERAL_HUGETLB
1659 config ARM_MODULE_PLTS
1660 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1664 Allocate PLTs when loading modules so that jumps and calls whose
1665 targets are too far away for their relative offsets to be encoded
1666 in the instructions themselves can be bounced via veneers in the
1667 module's PLT. This allows modules to be allocated in the generic
1668 vmalloc area after the dedicated module memory area has been
1669 exhausted. The modules will use slightly more memory, but after
1670 rounding up to page size, the actual memory footprint is usually
1673 Disabling this is usually safe for small single-platform
1674 configurations. If unsure, say y.
1676 config FORCE_MAX_ZONEORDER
1677 int "Maximum zone order"
1678 default "12" if SOC_AM33XX
1679 default "9" if SA1111 || ARCH_EFM32
1682 The kernel memory allocator divides physically contiguous memory
1683 blocks into "zones", where each zone is a power of two number of
1684 pages. This option selects the largest power of two that the kernel
1685 keeps in the memory allocator. If you need to allocate very large
1686 blocks of physically contiguous memory, then you may need to
1687 increase this value.
1689 This config option is actually maximum order plus one. For example,
1690 a value of 11 means that the largest free memory block is 2^10 pages.
1692 config ALIGNMENT_TRAP
1694 depends on CPU_CP15_MMU
1695 default y if !ARCH_EBSA110
1696 select HAVE_PROC_CPU if PROC_FS
1698 ARM processors cannot fetch/store information which is not
1699 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1700 address divisible by 4. On 32-bit ARM processors, these non-aligned
1701 fetch/store instructions will be emulated in software if you say
1702 here, which has a severe performance impact. This is necessary for
1703 correct operation of some network protocols. With an IP-only
1704 configuration it is safe to say N, otherwise say Y.
1706 config UACCESS_WITH_MEMCPY
1707 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1709 default y if CPU_FEROCEON
1711 Implement faster copy_to_user and clear_user methods for CPU
1712 cores where a 8-word STM instruction give significantly higher
1713 memory write throughput than a sequence of individual 32bit stores.
1715 A possible side effect is a slight increase in scheduling latency
1716 between threads sharing the same address space if they invoke
1717 such copy operations with large buffers.
1719 However, if the CPU data cache is using a write-allocate mode,
1720 this option is unlikely to provide any performance gain.
1724 prompt "Enable seccomp to safely compute untrusted bytecode"
1726 This kernel feature is useful for number crunching applications
1727 that may need to compute untrusted bytecode during their
1728 execution. By using pipes or other transports made available to
1729 the process as file descriptors supporting the read/write
1730 syscalls, it's possible to isolate those applications in
1731 their own address space using seccomp. Once seccomp is
1732 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1733 and the task is only allowed to execute a few safe syscalls
1734 defined by each seccomp mode.
1737 bool "Enable paravirtualization code"
1739 This changes the kernel so it can modify itself when it is run
1740 under a hypervisor, potentially improving performance significantly
1741 over full virtualization.
1743 config PARAVIRT_TIME_ACCOUNTING
1744 bool "Paravirtual steal time accounting"
1747 Select this option to enable fine granularity task steal time
1748 accounting. Time spent executing other tasks in parallel with
1749 the current vCPU is discounted from the vCPU power. To account for
1750 that, there can be a small performance impact.
1752 If in doubt, say N here.
1759 bool "Xen guest support on ARM"
1760 depends on ARM && AEABI && OF
1761 depends on CPU_V7 && !CPU_V6
1762 depends on !GENERIC_ATOMIC64
1764 select ARCH_DMA_ADDR_T_64BIT
1770 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1772 config STACKPROTECTOR_PER_TASK
1773 bool "Use a unique stack canary value for each task"
1774 depends on GCC_PLUGINS && STACKPROTECTOR && SMP && !XIP_DEFLATED_DATA
1775 select GCC_PLUGIN_ARM_SSP_PER_TASK
1778 Due to the fact that GCC uses an ordinary symbol reference from
1779 which to load the value of the stack canary, this value can only
1780 change at reboot time on SMP systems, and all tasks running in the
1781 kernel's address space are forced to use the same canary value for
1782 the entire duration that the system is up.
1784 Enable this option to switch to a different method that uses a
1785 different canary value for each task.
1792 bool "Flattened Device Tree support"
1796 Include support for flattened device tree machine descriptions.
1799 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1802 This is the traditional way of passing data to the kernel at boot
1803 time. If you are solely relying on the flattened device tree (or
1804 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1805 to remove ATAGS support from your kernel binary. If unsure,
1808 config DEPRECATED_PARAM_STRUCT
1809 bool "Provide old way to pass kernel parameters"
1812 This was deprecated in 2001 and announced to live on for 5 years.
1813 Some old boot loaders still use this way.
1815 # Compressed boot loader in ROM. Yes, we really want to ask about
1816 # TEXT and BSS so we preserve their values in the config files.
1817 config ZBOOT_ROM_TEXT
1818 hex "Compressed ROM boot loader base address"
1821 The physical address at which the ROM-able zImage is to be
1822 placed in the target. Platforms which normally make use of
1823 ROM-able zImage formats normally set this to a suitable
1824 value in their defconfig file.
1826 If ZBOOT_ROM is not enabled, this has no effect.
1828 config ZBOOT_ROM_BSS
1829 hex "Compressed ROM boot loader BSS address"
1832 The base address of an area of read/write memory in the target
1833 for the ROM-able zImage which must be available while the
1834 decompressor is running. It must be large enough to hold the
1835 entire decompressed kernel plus an additional 128 KiB.
1836 Platforms which normally make use of ROM-able zImage formats
1837 normally set this to a suitable value in their defconfig file.
1839 If ZBOOT_ROM is not enabled, this has no effect.
1842 bool "Compressed boot loader in ROM/flash"
1843 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1844 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1846 Say Y here if you intend to execute your compressed kernel image
1847 (zImage) directly from ROM or flash. If unsure, say N.
1849 config ARM_APPENDED_DTB
1850 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1853 With this option, the boot code will look for a device tree binary
1854 (DTB) appended to zImage
1855 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1857 This is meant as a backward compatibility convenience for those
1858 systems with a bootloader that can't be upgraded to accommodate
1859 the documented boot protocol using a device tree.
1861 Beware that there is very little in terms of protection against
1862 this option being confused by leftover garbage in memory that might
1863 look like a DTB header after a reboot if no actual DTB is appended
1864 to zImage. Do not leave this option active in a production kernel
1865 if you don't intend to always append a DTB. Proper passing of the
1866 location into r2 of a bootloader provided DTB is always preferable
1869 config ARM_ATAG_DTB_COMPAT
1870 bool "Supplement the appended DTB with traditional ATAG information"
1871 depends on ARM_APPENDED_DTB
1873 Some old bootloaders can't be updated to a DTB capable one, yet
1874 they provide ATAGs with memory configuration, the ramdisk address,
1875 the kernel cmdline string, etc. Such information is dynamically
1876 provided by the bootloader and can't always be stored in a static
1877 DTB. To allow a device tree enabled kernel to be used with such
1878 bootloaders, this option allows zImage to extract the information
1879 from the ATAG list and store it at run time into the appended DTB.
1882 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1883 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1885 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1886 bool "Use bootloader kernel arguments if available"
1888 Uses the command-line options passed by the boot loader instead of
1889 the device tree bootargs property. If the boot loader doesn't provide
1890 any, the device tree bootargs property will be used.
1892 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1893 bool "Extend with bootloader kernel arguments"
1895 The command-line arguments provided by the boot loader will be
1896 appended to the the device tree bootargs property.
1901 string "Default kernel command string"
1904 On some architectures (EBSA110 and CATS), there is currently no way
1905 for the boot loader to pass arguments to the kernel. For these
1906 architectures, you should supply some command-line options at build
1907 time by entering them here. As a minimum, you should specify the
1908 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1911 prompt "Kernel command line type" if CMDLINE != ""
1912 default CMDLINE_FROM_BOOTLOADER
1915 config CMDLINE_FROM_BOOTLOADER
1916 bool "Use bootloader kernel arguments if available"
1918 Uses the command-line options passed by the boot loader. If
1919 the boot loader doesn't provide any, the default kernel command
1920 string provided in CMDLINE will be used.
1922 config CMDLINE_EXTEND
1923 bool "Extend bootloader kernel arguments"
1925 The command-line arguments provided by the boot loader will be
1926 appended to the default kernel command string.
1928 config CMDLINE_FORCE
1929 bool "Always use the default kernel command string"
1931 Always use the default kernel command string, even if the boot
1932 loader passes other arguments to the kernel.
1933 This is useful if you cannot or don't want to change the
1934 command-line options your boot loader passes to the kernel.
1938 bool "Kernel Execute-In-Place from ROM"
1939 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1941 Execute-In-Place allows the kernel to run from non-volatile storage
1942 directly addressable by the CPU, such as NOR flash. This saves RAM
1943 space since the text section of the kernel is not loaded from flash
1944 to RAM. Read-write sections, such as the data section and stack,
1945 are still copied to RAM. The XIP kernel is not compressed since
1946 it has to run directly from flash, so it will take more space to
1947 store it. The flash address used to link the kernel object files,
1948 and for storing it, is configuration dependent. Therefore, if you
1949 say Y here, you must know the proper physical address where to
1950 store the kernel image depending on your own flash memory usage.
1952 Also note that the make target becomes "make xipImage" rather than
1953 "make zImage" or "make Image". The final kernel binary to put in
1954 ROM memory will be arch/arm/boot/xipImage.
1958 config XIP_PHYS_ADDR
1959 hex "XIP Kernel Physical Location"
1960 depends on XIP_KERNEL
1961 default "0x00080000"
1963 This is the physical address in your flash memory the kernel will
1964 be linked for and stored to. This address is dependent on your
1967 config XIP_DEFLATED_DATA
1968 bool "Store kernel .data section compressed in ROM"
1969 depends on XIP_KERNEL
1972 Before the kernel is actually executed, its .data section has to be
1973 copied to RAM from ROM. This option allows for storing that data
1974 in compressed form and decompressed to RAM rather than merely being
1975 copied, saving some precious ROM space. A possible drawback is a
1976 slightly longer boot delay.
1979 bool "Kexec system call (EXPERIMENTAL)"
1980 depends on (!SMP || PM_SLEEP_SMP)
1984 kexec is a system call that implements the ability to shutdown your
1985 current kernel, and to start another kernel. It is like a reboot
1986 but it is independent of the system firmware. And like a reboot
1987 you can start any kernel with it, not just Linux.
1989 It is an ongoing process to be certain the hardware in a machine
1990 is properly shutdown, so do not be surprised if this code does not
1991 initially work for you.
1994 bool "Export atags in procfs"
1995 depends on ATAGS && KEXEC
1998 Should the atags used to boot the kernel be exported in an "atags"
1999 file in procfs. Useful with kexec.
2002 bool "Build kdump crash kernel (EXPERIMENTAL)"
2004 Generate crash dump after being started by kexec. This should
2005 be normally only set in special crash dump kernels which are
2006 loaded in the main kernel with kexec-tools into a specially
2007 reserved region and then later executed after a crash by
2008 kdump/kexec. The crash dump kernel must be compiled to a
2009 memory address not used by the main kernel
2011 For more details see Documentation/kdump/kdump.txt
2013 config AUTO_ZRELADDR
2014 bool "Auto calculation of the decompressed kernel image address"
2016 ZRELADDR is the physical address where the decompressed kernel
2017 image will be placed. If AUTO_ZRELADDR is selected, the address
2018 will be determined at run-time by masking the current IP with
2019 0xf8000000. This assumes the zImage being placed in the first 128MB
2020 from start of memory.
2026 bool "UEFI runtime support"
2027 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
2029 select EFI_PARAMS_FROM_FDT
2032 select EFI_RUNTIME_WRAPPERS
2034 This option provides support for runtime services provided
2035 by UEFI firmware (such as non-volatile variables, realtime
2036 clock, and platform reset). A UEFI stub is also provided to
2037 allow the kernel to be booted as an EFI application. This
2038 is only useful for kernels that may run on systems that have
2042 bool "Enable support for SMBIOS (DMI) tables"
2046 This enables SMBIOS/DMI feature for systems.
2048 This option is only useful on systems that have UEFI firmware.
2049 However, even with this option, the resultant kernel should
2050 continue to boot on existing non-UEFI platforms.
2052 NOTE: This does *NOT* enable or encourage the use of DMI quirks,
2053 i.e., the the practice of identifying the platform via DMI to
2054 decide whether certain workarounds for buggy hardware and/or
2055 firmware need to be enabled. This would require the DMI subsystem
2056 to be enabled much earlier than we do on ARM, which is non-trivial.
2060 menu "CPU Power Management"
2062 source "drivers/cpufreq/Kconfig"
2064 source "drivers/cpuidle/Kconfig"
2068 menu "Floating point emulation"
2070 comment "At least one emulation must be selected"
2073 bool "NWFPE math emulation"
2074 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2076 Say Y to include the NWFPE floating point emulator in the kernel.
2077 This is necessary to run most binaries. Linux does not currently
2078 support floating point hardware so you need to say Y here even if
2079 your machine has an FPA or floating point co-processor podule.
2081 You may say N here if you are going to load the Acorn FPEmulator
2082 early in the bootup.
2085 bool "Support extended precision"
2086 depends on FPE_NWFPE
2088 Say Y to include 80-bit support in the kernel floating-point
2089 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2090 Note that gcc does not generate 80-bit operations by default,
2091 so in most cases this option only enlarges the size of the
2092 floating point emulator without any good reason.
2094 You almost surely want to say N here.
2097 bool "FastFPE math emulation (EXPERIMENTAL)"
2098 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2100 Say Y here to include the FAST floating point emulator in the kernel.
2101 This is an experimental much faster emulator which now also has full
2102 precision for the mantissa. It does not support any exceptions.
2103 It is very simple, and approximately 3-6 times faster than NWFPE.
2105 It should be sufficient for most programs. It may be not suitable
2106 for scientific calculations, but you have to check this for yourself.
2107 If you do not feel you need a faster FP emulation you should better
2111 bool "VFP-format floating point maths"
2112 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2114 Say Y to include VFP support code in the kernel. This is needed
2115 if your hardware includes a VFP unit.
2117 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2118 release notes and additional status information.
2120 Say N if your target does not have VFP hardware.
2128 bool "Advanced SIMD (NEON) Extension support"
2129 depends on VFPv3 && CPU_V7
2131 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2134 config KERNEL_MODE_NEON
2135 bool "Support for NEON in kernel mode"
2136 depends on NEON && AEABI
2138 Say Y to include support for NEON in kernel mode.
2142 menu "Power management options"
2144 source "kernel/power/Kconfig"
2146 config ARCH_SUSPEND_POSSIBLE
2147 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2148 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2151 config ARM_CPU_SUSPEND
2152 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW
2153 depends on ARCH_SUSPEND_POSSIBLE
2155 config ARCH_HIBERNATION_POSSIBLE
2158 default y if ARCH_SUSPEND_POSSIBLE
2162 source "drivers/firmware/Kconfig"
2165 source "arch/arm/crypto/Kconfig"
2168 source "arch/arm/kvm/Kconfig"