2 # For a description of the syntax of this configuration file,
3 # see Documentation/kbuild/kconfig-language.txt.
6 menuconfig ARC_PLAT_EZNPS
7 bool "\"EZchip\" ARC dev platform"
11 select EZCHIP_NPS_MANAGEMENT_ENET if ETHERNET
13 Support for EZchip development platforms,
14 based on ARC700 cores.
15 We handle few flavors:
16 - Hardware Emulator AKA HE which is FPGA based chassis
17 - Simulator based on MetaWare nSIM
18 - NPS400 chip based on ASIC
21 bool "ARC-EZchip MTM Extensions"
22 select CPUMASK_OFFSTACK
23 depends on ARC_PLAT_EZNPS && SMP
26 Here we add new hierarchy for CPUs topology.
30 At the new thread level each CPU represent one HW thread.
31 At highest hierarchy each core contain 16 threads,
32 any of them seem like CPU from Linux point of view.
33 All threads within same core share the execution unit of the
34 core and HW scheduler round robin between them.
36 config EZNPS_MEM_ERROR_ALIGN
37 bool "ARC-EZchip Memory error as an exception"
38 depends on EZNPS_MTM_EXT
41 On the real chip of the NPS, user memory errors are handled
42 as a machine check exception, which is fatal, whereas on
43 simulator platform for NPS, is handled as a Level 2 interrupt
44 (just a stock ARC700) which is recoverable. This option makes
45 simulator behave like hardware.
47 config EZNPS_SHARED_AUX_REGS
48 bool "ARC-EZchip Shared Auxiliary Registers Per Core"
49 depends on ARC_PLAT_EZNPS
52 On the real chip of the NPS, auxiliary registers are shared between
53 all the cpus of the core, whereas on simulator platform for NPS,
54 each cpu has a different set of auxiliary registers. Configuration
55 should be unset if auxiliary registers are not shared between the cpus
56 of the core, so there will be a need to initialize them per cpu.