arch/arc/kernel/setup.c

   1 /*
   2  * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #include <linux/seq_file.h>
  10 #include <linux/fs.h>
  11 #include <linux/delay.h>
  12 #include <linux/root_dev.h>
  13 #include <linux/clk.h>
  14 #include <linux/clk-provider.h>
  15 #include <linux/clocksource.h>
  16 #include <linux/console.h>
  17 #include <linux/module.h>
  18 #include <linux/cpu.h>
  19 #include <linux/of_fdt.h>
  20 #include <linux/of.h>
  21 #include <linux/cache.h>
  22 #include <uapi/linux/mount.h>
  23 #include <asm/sections.h>
  24 #include <asm/arcregs.h>
  25 #include <asm/tlb.h>
  26 #include <asm/setup.h>
  27 #include <asm/page.h>
  28 #include <asm/irq.h>
  29 #include <asm/unwind.h>
  30 #include <asm/mach_desc.h>
  31 #include <asm/smp.h>
  32
  33 #define FIX_PTR(x)  __asm__ __volatile__(";" : "+r"(x))
  34
  35 unsigned int intr_to_DE_cnt;
  36
  37 /* Part of U-boot ABI: see head.S */
  38 int __initdata uboot_tag;
  39 int __initdata uboot_magic;
  40 char __initdata *uboot_arg;
  41
  42 const struct machine_desc *machine_desc;
  43
  44 struct task_struct *_current_task[NR_CPUS];     /* For stack switching */
  45
  46 struct cpuinfo_arc cpuinfo_arc700[NR_CPUS];
  47
  48 static const struct id_to_str arc_legacy_rel[] = {
  49         /* ID.ARCVER,   Release */
  50 #ifdef CONFIG_ISA_ARCOMPACT
  51         { 0x34,         "R4.10"},
  52         { 0x35,         "R4.11"},
  53 #else
  54         { 0x51,         "R2.0" },
  55         { 0x52,         "R2.1" },
  56         { 0x53,         "R3.0" },
  57 #endif
  58         { 0x00,         NULL   }
  59 };
  60
  61 static const struct id_to_str arc_cpu_rel[] = {
  62         /* UARCH.MAJOR, Release */
  63         {  0,           "R3.10a"},
  64         {  1,           "R3.50a"},
  65         {  0xFF,        NULL   }
  66 };
  67
  68 static void read_decode_ccm_bcr(struct cpuinfo_arc *cpu)
  69 {
  70         if (is_isa_arcompact()) {
  71                 struct bcr_iccm_arcompact iccm;
  72                 struct bcr_dccm_arcompact dccm;
  73
  74                 READ_BCR(ARC_REG_ICCM_BUILD, iccm);
  75                 if (iccm.ver) {
  76                         cpu->iccm.sz = 4096 << iccm.sz; /* 8K to 512K */
  77                         cpu->iccm.base_addr = iccm.base << 16;
  78                 }
  79
  80                 READ_BCR(ARC_REG_DCCM_BUILD, dccm);
  81                 if (dccm.ver) {
  82                         unsigned long base;
  83                         cpu->dccm.sz = 2048 << dccm.sz; /* 2K to 256K */
  84
  85                         base = read_aux_reg(ARC_REG_DCCM_BASE_BUILD);
  86                         cpu->dccm.base_addr = base & ~0xF;
  87                 }
  88         } else {
  89                 struct bcr_iccm_arcv2 iccm;
  90                 struct bcr_dccm_arcv2 dccm;
  91                 unsigned long region;
  92
  93                 READ_BCR(ARC_REG_ICCM_BUILD, iccm);
  94                 if (iccm.ver) {
  95                         cpu->iccm.sz = 256 << iccm.sz00;        /* 512B to 16M */
  96                         if (iccm.sz00 == 0xF && iccm.sz01 > 0)
  97                                 cpu->iccm.sz <<= iccm.sz01;
  98
  99                         region = read_aux_reg(ARC_REG_AUX_ICCM);
 100                         cpu->iccm.base_addr = region & 0xF0000000;
 101                 }
 102
 103                 READ_BCR(ARC_REG_DCCM_BUILD, dccm);
 104                 if (dccm.ver) {
 105                         cpu->dccm.sz = 256 << dccm.sz0;
 106                         if (dccm.sz0 == 0xF && dccm.sz1 > 0)
 107                                 cpu->dccm.sz <<= dccm.sz1;
 108
 109                         region = read_aux_reg(ARC_REG_AUX_DCCM);
 110                         cpu->dccm.base_addr = region & 0xF0000000;
 111                 }
 112         }
 113 }
 114
 115 static void decode_arc_core(struct cpuinfo_arc *cpu)
 116 {
 117         struct bcr_uarch_build_arcv2 uarch;
 118         const struct id_to_str *tbl;
 119
 120         /*
 121          * Up until (including) the first core4 release (0x54) things were
 122          * simple: AUX IDENTITY.ARCVER was sufficient to identify arc family
 123          * and release: 0x50 to 0x53 was HS38, 0x54 was HS48 (dual issue)
 124          */
 125
 126         if (cpu->core.family < 0x54) { /* includes arc700 */
 127
 128                 for (tbl = &arc_legacy_rel[0]; tbl->id != 0; tbl++) {
 129                         if (cpu->core.family == tbl->id) {
 130                                 cpu->release = tbl->str;
 131                                 break;
 132                         }
 133                 }
 134
 135                 if (is_isa_arcompact())
 136                         cpu->name = "ARC700";
 137                 else if (tbl->str)
 138                         cpu->name = "HS38";
 139                 else
 140                         cpu->name = cpu->release = "Unknown";
 141
 142                 return;
 143         }
 144
 145         /*
 146          * However the subsequent HS release (same 0x54) allow HS38 or HS48
 147          * configurations and encode this info in a different BCR.
 148          * The BCR was introduced in 0x54 so can't be read unconditionally.
 149          */
 150
 151         READ_BCR(ARC_REG_MICRO_ARCH_BCR, uarch);
 152
 153         if (uarch.prod == 4) {
 154                 cpu->name = "HS48";
 155                 cpu->extn.dual = 1;
 156
 157         } else {
 158                 cpu->name = "HS38";
 159         }
 160
 161         for (tbl = &arc_cpu_rel[0]; tbl->id != 0xFF; tbl++) {
 162                 if (uarch.maj == tbl->id) {
 163                         cpu->release = tbl->str;
 164                         break;
 165                 }
 166         }
 167 }
 168
 169 static void read_arc_build_cfg_regs(void)
 170 {
 171         struct bcr_timer timer;
 172         struct bcr_generic bcr;
 173         struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()];
 174         struct bcr_isa_arcv2 isa;
 175         struct bcr_actionpoint ap;
 176
 177         FIX_PTR(cpu);
 178
 179         READ_BCR(AUX_IDENTITY, cpu->core);
 180         decode_arc_core(cpu);
 181
 182         READ_BCR(ARC_REG_TIMERS_BCR, timer);
 183         cpu->extn.timer0 = timer.t0;
 184         cpu->extn.timer1 = timer.t1;
 185         cpu->extn.rtc = timer.rtc;
 186
 187         cpu->vec_base = read_aux_reg(AUX_INTR_VEC_BASE);
 188
 189         READ_BCR(ARC_REG_MUL_BCR, cpu->extn_mpy);
 190
 191         /* Read CCM BCRs for boot reporting even if not enabled in Kconfig */
 192         read_decode_ccm_bcr(cpu);
 193
 194         read_decode_mmu_bcr();
 195         read_decode_cache_bcr();
 196
 197         if (is_isa_arcompact()) {
 198                 struct bcr_fp_arcompact sp, dp;
 199                 struct bcr_bpu_arcompact bpu;
 200
 201                 READ_BCR(ARC_REG_FP_BCR, sp);
 202                 READ_BCR(ARC_REG_DPFP_BCR, dp);
 203                 cpu->extn.fpu_sp = sp.ver ? 1 : 0;
 204                 cpu->extn.fpu_dp = dp.ver ? 1 : 0;
 205
 206                 READ_BCR(ARC_REG_BPU_BCR, bpu);
 207                 cpu->bpu.ver = bpu.ver;
 208                 cpu->bpu.full = bpu.fam ? 1 : 0;
 209                 if (bpu.ent) {
 210                         cpu->bpu.num_cache = 256 << (bpu.ent - 1);
 211                         cpu->bpu.num_pred = 256 << (bpu.ent - 1);
 212                 }
 213         } else {
 214                 struct bcr_fp_arcv2 spdp;
 215                 struct bcr_bpu_arcv2 bpu;
 216
 217                 READ_BCR(ARC_REG_FP_V2_BCR, spdp);
 218                 cpu->extn.fpu_sp = spdp.sp ? 1 : 0;
 219                 cpu->extn.fpu_dp = spdp.dp ? 1 : 0;
 220
 221                 READ_BCR(ARC_REG_BPU_BCR, bpu);
 222                 cpu->bpu.ver = bpu.ver;
 223                 cpu->bpu.full = bpu.ft;
 224                 cpu->bpu.num_cache = 256 << bpu.bce;
 225                 cpu->bpu.num_pred = 2048 << bpu.pte;
 226                 cpu->bpu.ret_stk = 4 << bpu.rse;
 227
 228                 /* if dual issue hardware, is it enabled ? */
 229                 if (cpu->extn.dual) {
 230                         unsigned int exec_ctrl;
 231
 232                         READ_BCR(AUX_EXEC_CTRL, exec_ctrl);
 233                         cpu->extn.dual_enb = !(exec_ctrl & 1);
 234                 }
 235         }
 236
 237         READ_BCR(ARC_REG_AP_BCR, ap);
 238         if (ap.ver) {
 239                 cpu->extn.ap_num = 2 << ap.num;
 240                 cpu->extn.ap_full = !ap.min;
 241         }
 242
 243         READ_BCR(ARC_REG_SMART_BCR, bcr);
 244         cpu->extn.smart = bcr.ver ? 1 : 0;
 245
 246         READ_BCR(ARC_REG_RTT_BCR, bcr);
 247         cpu->extn.rtt = bcr.ver ? 1 : 0;
 248
 249         READ_BCR(ARC_REG_ISA_CFG_BCR, isa);
 250
 251         /* some hacks for lack of feature BCR info in old ARC700 cores */
 252         if (is_isa_arcompact()) {
 253                 if (!isa.ver)   /* ISA BCR absent, use Kconfig info */
 254                         cpu->isa.atomic = IS_ENABLED(CONFIG_ARC_HAS_LLSC);
 255                 else {
 256                         /* ARC700_BUILD only has 2 bits of isa info */
 257                         struct bcr_generic bcr = *(struct bcr_generic *)&isa;
 258                         cpu->isa.atomic = bcr.info & 1;
 259                 }
 260
 261                 cpu->isa.be = IS_ENABLED(CONFIG_CPU_BIG_ENDIAN);
 262
 263                  /* there's no direct way to distinguish 750 vs. 770 */
 264                 if (unlikely(cpu->core.family < 0x34 || cpu->mmu.ver < 3))
 265                         cpu->name = "ARC750";
 266         } else {
 267                 cpu->isa = isa;
 268         }
 269 }
 270
 271 static char *arc_cpu_mumbojumbo(int cpu_id, char *buf, int len)
 272 {
 273         struct cpuinfo_arc *cpu = &cpuinfo_arc700[cpu_id];
 274         struct bcr_identity *core = &cpu->core;
 275         char mpy_opt[16];
 276         int n = 0;
 277
 278         FIX_PTR(cpu);
 279
 280         n += scnprintf(buf + n, len - n,
 281                        "\nIDENTITY\t: ARCVER [%#02x] ARCNUM [%#02x] CHIPID [%#4x]\n",
 282                        core->family, core->cpu_id, core->chip_id);
 283
 284         n += scnprintf(buf + n, len - n, "processor [%d]\t: %s %s (%s ISA) %s%s%s\n",
 285                        cpu_id, cpu->name, cpu->release,
 286                        is_isa_arcompact() ? "ARCompact" : "ARCv2",
 287                        IS_AVAIL1(cpu->isa.be, "[Big-Endian]"),
 288                        IS_AVAIL3(cpu->extn.dual, cpu->extn.dual_enb, " Dual-Issue "));
 289
 290         n += scnprintf(buf + n, len - n, "Timers\t\t: %s%s%s%s%s%s\nISA Extn\t: ",
 291                        IS_AVAIL1(cpu->extn.timer0, "Timer0 "),
 292                        IS_AVAIL1(cpu->extn.timer1, "Timer1 "),
 293                        IS_AVAIL2(cpu->extn.rtc, "RTC [UP 64-bit] ", CONFIG_ARC_TIMERS_64BIT),
 294                        IS_AVAIL2(cpu->extn.gfrc, "GFRC [SMP 64-bit] ", CONFIG_ARC_TIMERS_64BIT));
 295
 296         if (cpu->extn_mpy.ver) {
 297                 if (is_isa_arcompact()) {
 298                         scnprintf(mpy_opt, 16, "mpy");
 299                 } else {
 300
 301                         int opt = 2;    /* stock MPY/MPYH */
 302
 303                         if (cpu->extn_mpy.dsp)  /* OPT 7-9 */
 304                                 opt = cpu->extn_mpy.dsp + 6;
 305
 306                         scnprintf(mpy_opt, 16, "mpy[opt %d] ", opt);
 307                 }
 308         }
 309
 310         n += scnprintf(buf + n, len - n, "%s%s%s%s%s%s%s%s\n",
 311                        IS_AVAIL2(cpu->isa.atomic, "atomic ", CONFIG_ARC_HAS_LLSC),
 312                        IS_AVAIL2(cpu->isa.ldd, "ll64 ", CONFIG_ARC_HAS_LL64),
 313                        IS_AVAIL2(cpu->isa.unalign, "unalign ", CONFIG_ARC_USE_UNALIGNED_MEM_ACCESS),
 314                        IS_AVAIL1(cpu->extn_mpy.ver, mpy_opt),
 315                        IS_AVAIL1(cpu->isa.div_rem, "div_rem "));
 316
 317         if (cpu->bpu.ver) {
 318                 n += scnprintf(buf + n, len - n,
 319                               "BPU\t\t: %s%s match, cache:%d, Predict Table:%d Return stk: %d",
 320                               IS_AVAIL1(cpu->bpu.full, "full"),
 321                               IS_AVAIL1(!cpu->bpu.full, "partial"),
 322                               cpu->bpu.num_cache, cpu->bpu.num_pred, cpu->bpu.ret_stk);
 323
 324                 if (is_isa_arcv2()) {
 325                         struct bcr_lpb lpb;
 326
 327                         READ_BCR(ARC_REG_LPB_BUILD, lpb);
 328                         if (lpb.ver) {
 329                                 unsigned int ctl;
 330                                 ctl = read_aux_reg(ARC_REG_LPB_CTRL);
 331
 332                                 n += scnprintf(buf + n, len - n, " Loop Buffer:%d %s",
 333                                                lpb.entries,
 334                                                IS_DISABLED_RUN(!ctl));
 335                         }
 336                 }
 337                 n += scnprintf(buf + n, len - n, "\n");
 338         }
 339
 340         return buf;
 341 }
 342
 343 static char *arc_extn_mumbojumbo(int cpu_id, char *buf, int len)
 344 {
 345         int n = 0;
 346         struct cpuinfo_arc *cpu = &cpuinfo_arc700[cpu_id];
 347
 348         FIX_PTR(cpu);
 349
 350         n += scnprintf(buf + n, len - n, "Vector Table\t: %#x\n", cpu->vec_base);
 351
 352         if (cpu->extn.fpu_sp || cpu->extn.fpu_dp)
 353                 n += scnprintf(buf + n, len - n, "FPU\t\t: %s%s\n",
 354                                IS_AVAIL1(cpu->extn.fpu_sp, "SP "),
 355                                IS_AVAIL1(cpu->extn.fpu_dp, "DP "));
 356
 357         if (cpu->extn.ap_num | cpu->extn.smart | cpu->extn.rtt) {
 358                 n += scnprintf(buf + n, len - n, "DEBUG\t\t: %s%s",
 359                                IS_AVAIL1(cpu->extn.smart, "smaRT "),
 360                                IS_AVAIL1(cpu->extn.rtt, "RTT "));
 361                 if (cpu->extn.ap_num) {
 362                         n += scnprintf(buf + n, len - n, "ActionPoint %d/%s",
 363                                        cpu->extn.ap_num,
 364                                        cpu->extn.ap_full ? "full":"min");
 365                 }
 366                 n += scnprintf(buf + n, len - n, "\n");
 367         }
 368
 369         if (cpu->dccm.sz || cpu->iccm.sz)
 370                 n += scnprintf(buf + n, len - n, "Extn [CCM]\t: DCCM @ %x, %d KB / ICCM: @ %x, %d KB\n",
 371                                cpu->dccm.base_addr, TO_KB(cpu->dccm.sz),
 372                                cpu->iccm.base_addr, TO_KB(cpu->iccm.sz));
 373
 374         if (is_isa_arcv2()) {
 375
 376                 /* Error Protection: ECC/Parity */
 377                 struct bcr_erp erp;
 378                 READ_BCR(ARC_REG_ERP_BUILD, erp);
 379
 380                 if (erp.ver) {
 381                         struct  ctl_erp ctl;
 382                         READ_BCR(ARC_REG_ERP_CTRL, ctl);
 383
 384                         /* inverted bits: 0 means enabled */
 385                         n += scnprintf(buf + n, len - n, "Extn [ECC]\t: %s%s%s%s%s%s\n",
 386                                 IS_AVAIL3(erp.ic,  !ctl.dpi, "IC "),
 387                                 IS_AVAIL3(erp.dc,  !ctl.dpd, "DC "),
 388                                 IS_AVAIL3(erp.mmu, !ctl.mpd, "MMU "));
 389                 }
 390         }
 391
 392         return buf;
 393 }
 394
 395 static void arc_chk_core_config(void)
 396 {
 397         struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()];
 398         int saved = 0, present = 0;
 399         char *opt_nm = NULL;
 400
 401         if (!cpu->extn.timer0)
 402                 panic("Timer0 is not present!\n");
 403
 404         if (!cpu->extn.timer1)
 405                 panic("Timer1 is not present!\n");
 406
 407 #ifdef CONFIG_ARC_HAS_DCCM
 408         /*
 409          * DCCM can be arbit placed in hardware.
 410          * Make sure it's placement/sz matches what Linux is built with
 411          */
 412         if ((unsigned int)__arc_dccm_base != cpu->dccm.base_addr)
 413                 panic("Linux built with incorrect DCCM Base address\n");
 414
 415         if (CONFIG_ARC_DCCM_SZ != cpu->dccm.sz)
 416                 panic("Linux built with incorrect DCCM Size\n");
 417 #endif
 418
 419 #ifdef CONFIG_ARC_HAS_ICCM
 420         if (CONFIG_ARC_ICCM_SZ != cpu->iccm.sz)
 421                 panic("Linux built with incorrect ICCM Size\n");
 422 #endif
 423
 424         /*
 425          * FP hardware/software config sanity
 426          * -If hardware present, kernel needs to save/restore FPU state
 427          * -If not, it will crash trying to save/restore the non-existant regs
 428          */
 429
 430         if (is_isa_arcompact()) {
 431                 opt_nm = "CONFIG_ARC_FPU_SAVE_RESTORE";
 432                 saved = IS_ENABLED(CONFIG_ARC_FPU_SAVE_RESTORE);
 433
 434                 /* only DPDP checked since SP has no arch visible regs */
 435                 present = cpu->extn.fpu_dp;
 436         } else {
 437                 opt_nm = "CONFIG_ARC_HAS_ACCL_REGS";
 438                 saved = IS_ENABLED(CONFIG_ARC_HAS_ACCL_REGS);
 439
 440                 /* Accumulator Low:High pair (r58:59) present if DSP MPY or FPU */
 441                 present = cpu->extn_mpy.dsp | cpu->extn.fpu_sp | cpu->extn.fpu_dp;
 442         }
 443
 444         if (present && !saved)
 445                 pr_warn("Enable %s for working apps\n", opt_nm);
 446         else if (!present && saved)
 447                 panic("Disable %s, hardware NOT present\n", opt_nm);
 448 }
 449
 450 /*
 451  * Initialize and setup the processor core
 452  * This is called by all the CPUs thus should not do special case stuff
 453  *    such as only for boot CPU etc
 454  */
 455
 456 void setup_processor(void)
 457 {
 458         char str[512];
 459         int cpu_id = smp_processor_id();
 460
 461         read_arc_build_cfg_regs();
 462         arc_init_IRQ();
 463
 464         pr_info("%s", arc_cpu_mumbojumbo(cpu_id, str, sizeof(str)));
 465
 466         arc_mmu_init();
 467         arc_cache_init();
 468
 469         pr_info("%s", arc_extn_mumbojumbo(cpu_id, str, sizeof(str)));
 470         pr_info("%s", arc_platform_smp_cpuinfo());
 471
 472         arc_chk_core_config();
 473 }
 474
 475 static inline bool uboot_arg_invalid(unsigned long addr)
 476 {
 477         /*
 478          * Check that it is a untranslated address (although MMU is not enabled
 479          * yet, it being a high address ensures this is not by fluke)
 480          */
 481         if (addr < PAGE_OFFSET)
 482                 return true;
 483
 484         /* Check that address doesn't clobber resident kernel image */
 485         return addr >= (unsigned long)_stext && addr <= (unsigned long)_end;
 486 }
 487
 488 #define IGNORE_ARGS             "Ignore U-boot args: "
 489
 490 /* uboot_tag values for U-boot - kernel ABI revision 0; see head.S */
 491 #define UBOOT_TAG_NONE          0
 492 #define UBOOT_TAG_CMDLINE       1
 493 #define UBOOT_TAG_DTB           2
 494 /* We always pass 0 as magic from U-boot */
 495 #define UBOOT_MAGIC_VALUE       0
 496
 497 void __init handle_uboot_args(void)
 498 {
 499         bool use_embedded_dtb = true;
 500         bool append_cmdline = false;
 501
 502         /* check that we know this tag */
 503         if (uboot_tag != UBOOT_TAG_NONE &&
 504             uboot_tag != UBOOT_TAG_CMDLINE &&
 505             uboot_tag != UBOOT_TAG_DTB) {
 506                 pr_warn(IGNORE_ARGS "invalid uboot tag: '%08x'\n", uboot_tag);
 507                 goto ignore_uboot_args;
 508         }
 509
 510         if (uboot_magic != UBOOT_MAGIC_VALUE) {
 511                 pr_warn(IGNORE_ARGS "non zero uboot magic\n");
 512                 goto ignore_uboot_args;
 513         }
 514
 515         if (uboot_tag != UBOOT_TAG_NONE &&
 516             uboot_arg_invalid((unsigned long)uboot_arg)) {
 517                 pr_warn(IGNORE_ARGS "invalid uboot arg: '%px'\n", uboot_arg);
 518                 goto ignore_uboot_args;
 519         }
 520
 521         /* see if U-boot passed an external Device Tree blob */
 522         if (uboot_tag == UBOOT_TAG_DTB) {
 523                 machine_desc = setup_machine_fdt((void *)uboot_arg);
 524
 525                 /* external Device Tree blob is invalid - use embedded one */
 526                 use_embedded_dtb = !machine_desc;
 527         }
 528
 529         if (uboot_tag == UBOOT_TAG_CMDLINE)
 530                 append_cmdline = true;
 531
 532 ignore_uboot_args:
 533
 534         if (use_embedded_dtb) {
 535                 machine_desc = setup_machine_fdt(__dtb_start);
 536                 if (!machine_desc)
 537                         panic("Embedded DT invalid\n");
 538         }
 539
 540         /*
 541          * NOTE: @boot_command_line is populated by setup_machine_fdt() so this
 542          * append processing can only happen after.
 543          */
 544         if (append_cmdline) {
 545                 /* Ensure a whitespace between the 2 cmdlines */
 546                 strlcat(boot_command_line, " ", COMMAND_LINE_SIZE);
 547                 strlcat(boot_command_line, uboot_arg, COMMAND_LINE_SIZE);
 548         }
 549 }
 550
 551 void __init setup_arch(char **cmdline_p)
 552 {
 553         handle_uboot_args();
 554
 555         /* Save unparsed command line copy for /proc/cmdline */
 556         *cmdline_p = boot_command_line;
 557
 558         /* To force early parsing of things like mem=xxx */
 559         parse_early_param();
 560
 561         /* Platform/board specific: e.g. early console registration */
 562         if (machine_desc->init_early)
 563                 machine_desc->init_early();
 564
 565         smp_init_cpus();
 566
 567         setup_processor();
 568         setup_arch_memory();
 569
 570         /* copy flat DT out of .init and then unflatten it */
 571         unflatten_and_copy_device_tree();
 572
 573         /* Can be issue if someone passes cmd line arg "ro"
 574          * But that is unlikely so keeping it as it is
 575          */
 576         root_mountflags &= ~MS_RDONLY;
 577
 578 #if defined(CONFIG_VT) && defined(CONFIG_DUMMY_CONSOLE)
 579         conswitchp = &dummy_con;
 580 #endif
 581
 582         arc_unwind_init();
 583 }
 584
 585 /*
 586  * Called from start_kernel() - boot CPU only
 587  */
 588 void __init time_init(void)
 589 {
 590         of_clk_init(NULL);
 591         timer_probe();
 592 }
 593
 594 static int __init customize_machine(void)
 595 {
 596         if (machine_desc->init_machine)
 597                 machine_desc->init_machine();
 598
 599         return 0;
 600 }
 601 arch_initcall(customize_machine);
 602
 603 static int __init init_late_machine(void)
 604 {
 605         if (machine_desc->init_late)
 606                 machine_desc->init_late();
 607
 608         return 0;
 609 }
 610 late_initcall(init_late_machine);
 611 /*
 612  *  Get CPU information for use by the procfs.
 613  */
 614
 615 #define cpu_to_ptr(c)   ((void *)(0xFFFF0000 | (unsigned int)(c)))
 616 #define ptr_to_cpu(p)   (~0xFFFF0000UL & (unsigned int)(p))
 617
 618 static int show_cpuinfo(struct seq_file *m, void *v)
 619 {
 620         char *str;
 621         int cpu_id = ptr_to_cpu(v);
 622         struct device *cpu_dev = get_cpu_device(cpu_id);
 623         struct clk *cpu_clk;
 624         unsigned long freq = 0;
 625
 626         if (!cpu_online(cpu_id)) {
 627                 seq_printf(m, "processor [%d]\t: Offline\n", cpu_id);
 628                 goto done;
 629         }
 630
 631         str = (char *)__get_free_page(GFP_KERNEL);
 632         if (!str)
 633                 goto done;
 634
 635         seq_printf(m, arc_cpu_mumbojumbo(cpu_id, str, PAGE_SIZE));
 636
 637         cpu_clk = clk_get(cpu_dev, NULL);
 638         if (IS_ERR(cpu_clk)) {
 639                 seq_printf(m, "CPU speed \t: Cannot get clock for processor [%d]\n",
 640                            cpu_id);
 641         } else {
 642                 freq = clk_get_rate(cpu_clk);
 643         }
 644         if (freq)
 645                 seq_printf(m, "CPU speed\t: %lu.%02lu Mhz\n",
 646                            freq / 1000000, (freq / 10000) % 100);
 647
 648         seq_printf(m, "Bogo MIPS\t: %lu.%02lu\n",
 649                    loops_per_jiffy / (500000 / HZ),
 650                    (loops_per_jiffy / (5000 / HZ)) % 100);
 651
 652         seq_printf(m, arc_mmu_mumbojumbo(cpu_id, str, PAGE_SIZE));
 653         seq_printf(m, arc_cache_mumbojumbo(cpu_id, str, PAGE_SIZE));
 654         seq_printf(m, arc_extn_mumbojumbo(cpu_id, str, PAGE_SIZE));
 655         seq_printf(m, arc_platform_smp_cpuinfo());
 656
 657         free_page((unsigned long)str);
 658 done:
 659         seq_printf(m, "\n");
 660
 661         return 0;
 662 }
 663
 664 static void *c_start(struct seq_file *m, loff_t *pos)
 665 {
 666         /*
 667          * Callback returns cpu-id to iterator for show routine, NULL to stop.
 668          * However since NULL is also a valid cpu-id (0), we use a round-about
 669          * way to pass it w/o having to kmalloc/free a 2 byte string.
 670          * Encode cpu-id as 0xFFcccc, which is decoded by show routine.
 671          */
 672         return *pos < nr_cpu_ids ? cpu_to_ptr(*pos) : NULL;
 673 }
 674
 675 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
 676 {
 677         ++*pos;
 678         return c_start(m, pos);
 679 }
 680
 681 static void c_stop(struct seq_file *m, void *v)
 682 {
 683 }
 684
 685 const struct seq_operations cpuinfo_op = {
 686         .start  = c_start,
 687         .next   = c_next,
 688         .stop   = c_stop,
 689         .show   = show_cpuinfo
 690 };
 691
 692 static DEFINE_PER_CPU(struct cpu, cpu_topology);
 693
 694 static int __init topology_init(void)
 695 {
 696         int cpu;
 697
 698         for_each_present_cpu(cpu)
 699             register_cpu(&per_cpu(cpu_topology, cpu), cpu);
 700
 701         return 0;
 702 }
 703
 704 subsys_initcall(topology_init);