arch/arc/boot/dts/nsim_hs.dts

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
   4  */
   5 /dts-v1/;
   6
   7 /include/ "skeleton_hs.dtsi"
   8
   9 / {
  10         model = "snps,nsim_hs";
  11         compatible = "snps,nsim_hs";
  12         #address-cells = <2>;
  13         #size-cells = <2>;
  14         interrupt-parent = <&core_intc>;
  15
  16         memory {
  17                 device_type = "memory";
  18                 /* CONFIG_LINUX_RAM_BASE needs to match low mem start */
  19                 reg = <0x0 0x80000000 0x0 0x20000000    /* 512 MB low mem */
  20                        0x1 0x00000000 0x0 0x40000000>;  /* 1 GB highmem */
  21         };
  22
  23         chosen {
  24                 bootargs = "earlycon=arc_uart,mmio32,0xc0fc1000,115200n8 console=ttyARC0,115200n8 print-fatal-signals=1";
  25         };
  26
  27         aliases {
  28                 serial0 = &arcuart0;
  29         };
  30
  31         fpga {
  32                 compatible = "simple-bus";
  33                 #address-cells = <1>;
  34                 #size-cells = <1>;
  35
  36                 /* only perip space at end of low mem accessible
  37                          bus addr,   parent bus addr, size */
  38                 ranges = <0x80000000 0x0 0x80000000 0x80000000>;
  39
  40                 core_clk: core_clk {
  41                         #clock-cells = <0>;
  42                         compatible = "fixed-clock";
  43                         clock-frequency = <80000000>;
  44                 };
  45
  46                 core_intc: core-interrupt-controller {
  47                         compatible = "snps,archs-intc";
  48                         interrupt-controller;
  49                         #interrupt-cells = <1>;
  50                 };
  51
  52                 arcuart0: serial@c0fc1000 {
  53                         compatible = "snps,arc-uart";
  54                         reg = <0xc0fc1000 0x100>;
  55                         interrupts = <24>;
  56                         clock-frequency = <80000000>;
  57                         current-speed = <115200>;
  58                         status = "okay";
  59                 };
  60
  61                 arcpct0: pct {
  62                         compatible = "snps,archs-pct";
  63                         #interrupt-cells = <1>;
  64                         interrupts = <20>;
  65                 };
  66         };
  67 };