Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
[sfrench/cifs-2.6.git] / arch / arc / boot / dts / hsdk.dts
1 /*
2  * Copyright (C) 2017 Synopsys, Inc. (www.synopsys.com)
3  *
4  * This program is free software; you can redistribute it and/or modify
5  * it under the terms of the GNU General Public License version 2 as
6  * published by the Free Software Foundation.
7  */
8
9 /*
10  * Device Tree for ARC HS Development Kit
11  */
12 /dts-v1/;
13
14 #include <dt-bindings/net/ti-dp83867.h>
15 #include <dt-bindings/reset/snps,hsdk-reset.h>
16
17 / {
18         model = "snps,hsdk";
19         compatible = "snps,hsdk";
20
21         #address-cells = <2>;
22         #size-cells = <2>;
23
24         chosen {
25                 bootargs = "earlycon=uart8250,mmio32,0xf0005000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
26         };
27
28         aliases {
29                 ethernet = &gmac;
30         };
31
32         cpus {
33                 #address-cells = <1>;
34                 #size-cells = <0>;
35
36                 cpu@0 {
37                         device_type = "cpu";
38                         compatible = "snps,archs38";
39                         reg = <0>;
40                         clocks = <&core_clk>;
41                 };
42
43                 cpu@1 {
44                         device_type = "cpu";
45                         compatible = "snps,archs38";
46                         reg = <1>;
47                         clocks = <&core_clk>;
48                 };
49
50                 cpu@2 {
51                         device_type = "cpu";
52                         compatible = "snps,archs38";
53                         reg = <2>;
54                         clocks = <&core_clk>;
55                 };
56
57                 cpu@3 {
58                         device_type = "cpu";
59                         compatible = "snps,archs38";
60                         reg = <3>;
61                         clocks = <&core_clk>;
62                 };
63         };
64
65         input_clk: input-clk {
66                 #clock-cells = <0>;
67                 compatible = "fixed-clock";
68                 clock-frequency = <33333333>;
69         };
70
71         cpu_intc: cpu-interrupt-controller {
72                 compatible = "snps,archs-intc";
73                 interrupt-controller;
74                 #interrupt-cells = <1>;
75         };
76
77         idu_intc: idu-interrupt-controller {
78                 compatible = "snps,archs-idu-intc";
79                 interrupt-controller;
80                 #interrupt-cells = <1>;
81                 interrupt-parent = <&cpu_intc>;
82         };
83
84         arcpct: pct {
85                 compatible = "snps,archs-pct";
86         };
87
88         /* TIMER0 with interrupt for clockevent */
89         timer {
90                 compatible = "snps,arc-timer";
91                 interrupts = <16>;
92                 interrupt-parent = <&cpu_intc>;
93                 clocks = <&core_clk>;
94         };
95
96         /* 64-bit Global Free Running Counter */
97         gfrc {
98                 compatible = "snps,archs-timer-gfrc";
99                 clocks = <&core_clk>;
100         };
101
102         soc {
103                 compatible = "simple-bus";
104                 #address-cells = <1>;
105                 #size-cells = <1>;
106                 interrupt-parent = <&idu_intc>;
107
108                 ranges = <0x00000000 0x0 0xf0000000 0x10000000>;
109
110                 cgu_rst: reset-controller@8a0 {
111                         compatible = "snps,hsdk-reset";
112                         #reset-cells = <1>;
113                         reg = <0x8a0 0x4>, <0xff0 0x4>;
114                 };
115
116                 core_clk: core-clk@0 {
117                         compatible = "snps,hsdk-core-pll-clock";
118                         reg = <0x00 0x10>, <0x14b8 0x4>;
119                         #clock-cells = <0>;
120                         clocks = <&input_clk>;
121
122                         /*
123                          * Set initial core pll output frequency to 1GHz.
124                          * It will be applied at the core pll driver probing
125                          * on early boot.
126                          */
127                         assigned-clocks = <&core_clk>;
128                         assigned-clock-rates = <1000000000>;
129                 };
130
131                 serial: serial@5000 {
132                         compatible = "snps,dw-apb-uart";
133                         reg = <0x5000 0x100>;
134                         clock-frequency = <33330000>;
135                         interrupts = <6>;
136                         baud = <115200>;
137                         reg-shift = <2>;
138                         reg-io-width = <4>;
139                 };
140
141                 gmacclk: gmacclk {
142                         compatible = "fixed-clock";
143                         clock-frequency = <400000000>;
144                         #clock-cells = <0>;
145                 };
146
147                 mmcclk_ciu: mmcclk-ciu {
148                         compatible = "fixed-clock";
149                         /*
150                          * DW sdio controller has external ciu clock divider
151                          * controlled via register in SDIO IP. Due to its
152                          * unexpected default value (it should divide by 1
153                          * but it divides by 8) SDIO IP uses wrong clock and
154                          * works unstable (see STAR 9001204800)
155                          * We switched to the minimum possible value of the
156                          * divisor (div-by-2) in HSDK platform code.
157                          * So add temporary fix and change clock frequency
158                          * to 50000000 Hz until we fix dw sdio driver itself.
159                          */
160                         clock-frequency = <50000000>;
161                         #clock-cells = <0>;
162                 };
163
164                 mmcclk_biu: mmcclk-biu {
165                         compatible = "fixed-clock";
166                         clock-frequency = <400000000>;
167                         #clock-cells = <0>;
168                 };
169
170                 dmac_core_clk: dmac-core-clk {
171                         compatible = "fixed-clock";
172                         clock-frequency = <400000000>;
173                         #clock-cells = <0>;
174                 };
175
176                 dmac_cfg_clk: dmac-gpu-cfg-clk {
177                         compatible = "fixed-clock";
178                         clock-frequency = <200000000>;
179                         #clock-cells = <0>;
180                 };
181
182                 gmac: ethernet@8000 {
183                         #interrupt-cells = <1>;
184                         compatible = "snps,dwmac";
185                         reg = <0x8000 0x2000>;
186                         interrupts = <10>;
187                         interrupt-names = "macirq";
188                         phy-mode = "rgmii";
189                         snps,pbl = <32>;
190                         clocks = <&gmacclk>;
191                         clock-names = "stmmaceth";
192                         phy-handle = <&phy0>;
193                         resets = <&cgu_rst HSDK_ETH_RESET>;
194                         reset-names = "stmmaceth";
195                         mac-address = [00 00 00 00 00 00]; /* Filled in by U-Boot */
196                         dma-coherent;
197
198                         mdio {
199                                 #address-cells = <1>;
200                                 #size-cells = <0>;
201                                 compatible = "snps,dwmac-mdio";
202                                 phy0: ethernet-phy@0 {
203                                         reg = <0>;
204                                         ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
205                                         ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
206                                         ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
207                                 };
208                         };
209                 };
210
211                 ohci@60000 {
212                         compatible = "snps,hsdk-v1.0-ohci", "generic-ohci";
213                         reg = <0x60000 0x100>;
214                         interrupts = <15>;
215                         resets = <&cgu_rst HSDK_USB_RESET>;
216                         dma-coherent;
217                 };
218
219                 ehci@40000 {
220                         compatible = "snps,hsdk-v1.0-ehci", "generic-ehci";
221                         reg = <0x40000 0x100>;
222                         interrupts = <15>;
223                         resets = <&cgu_rst HSDK_USB_RESET>;
224                         dma-coherent;
225                 };
226
227                 mmc@a000 {
228                         compatible = "altr,socfpga-dw-mshc";
229                         reg = <0xa000 0x400>;
230                         num-slots = <1>;
231                         fifo-depth = <16>;
232                         card-detect-delay = <200>;
233                         clocks = <&mmcclk_biu>, <&mmcclk_ciu>;
234                         clock-names = "biu", "ciu";
235                         interrupts = <12>;
236                         bus-width = <4>;
237                         dma-coherent;
238                 };
239
240                 gpio: gpio@3000 {
241                         compatible = "snps,dw-apb-gpio";
242                         reg = <0x3000 0x20>;
243                         #address-cells = <1>;
244                         #size-cells = <0>;
245
246                         gpio_port_a: gpio-controller@0 {
247                                 compatible = "snps,dw-apb-gpio-port";
248                                 gpio-controller;
249                                 #gpio-cells = <2>;
250                                 snps,nr-gpios = <24>;
251                                 reg = <0>;
252                         };
253                 };
254
255                 dmac: dmac@80000 {
256                         compatible = "snps,axi-dma-1.01a";
257                         reg = <0x80000 0x400>;
258                         interrupts = <27>;
259                         clocks = <&dmac_core_clk>, <&dmac_cfg_clk>;
260                         clock-names = "core-clk", "cfgr-clk";
261
262                         dma-channels = <4>;
263                         snps,dma-masters = <2>;
264                         snps,data-width = <3>;
265                         snps,block-size = <4096 4096 4096 4096>;
266                         snps,priority = <0 1 2 3>;
267                         snps,axi-max-burst-len = <16>;
268                 };
269         };
270
271         memory@80000000 {
272                 #address-cells = <2>;
273                 #size-cells = <2>;
274                 device_type = "memory";
275                 reg = <0x0 0x80000000 0x0 0x40000000>;  /* 1 GB lowmem */
276                 /*     0x1 0x00000000 0x0 0x40000000>;     1 GB highmem */
277         };
278 };