arch/arc/boot/dts/axs10x_mb.dtsi

   1 /*
   2  * Support for peripherals on the AXS10x mainboard
   3  *
   4  * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 / {
  12         axs10x_mb {
  13                 compatible = "simple-bus";
  14                 #address-cells = <1>;
  15                 #size-cells = <1>;
  16                 ranges = <0x00000000 0xe0000000 0x10000000>;
  17                 interrupt-parent = <&mb_intc>;
  18
  19                 i2sclk: i2sclk@100a0 {
  20                         compatible = "snps,axs10x-i2s-pll-clock";
  21                         reg = <0x100a0 0x10>;
  22                         clocks = <&i2spll_clk>;
  23                         #clock-cells = <0>;
  24                 };
  25
  26                 clocks {
  27                         i2spll_clk: i2spll_clk {
  28                                 compatible = "fixed-clock";
  29                                 clock-frequency = <27000000>;
  30                                 #clock-cells = <0>;
  31                         };
  32
  33                         i2cclk: i2cclk {
  34                                 compatible = "fixed-clock";
  35                                 clock-frequency = <50000000>;
  36                                 #clock-cells = <0>;
  37                         };
  38
  39                         apbclk: apbclk {
  40                                 compatible = "fixed-clock";
  41                                 clock-frequency = <50000000>;
  42                                 #clock-cells = <0>;
  43                         };
  44
  45                         mmcclk: mmcclk {
  46                                 compatible = "fixed-clock";
  47                                 clock-frequency = <50000000>;
  48                                 #clock-cells = <0>;
  49                         };
  50
  51                         pguclk: pguclk {
  52                                 #clock-cells = <0>;
  53                                 compatible = "fixed-clock";
  54                                 clock-frequency = <74440000>;
  55                         };
  56                 };
  57
  58                 ethernet@0x18000 {
  59                         #interrupt-cells = <1>;
  60                         compatible = "snps,dwmac";
  61                         reg = < 0x18000 0x2000 >;
  62                         interrupts = < 4 >;
  63                         interrupt-names = "macirq";
  64                         phy-mode = "rgmii";
  65                         snps,pbl = < 32 >;
  66                         clocks = <&apbclk>;
  67                         clock-names = "stmmaceth";
  68                         max-speed = <100>;
  69                 };
  70
  71                 ehci@0x40000 {
  72                         compatible = "generic-ehci";
  73                         reg = < 0x40000 0x100 >;
  74                         interrupts = < 8 >;
  75                 };
  76
  77                 ohci@0x60000 {
  78                         compatible = "generic-ohci";
  79                         reg = < 0x60000 0x100 >;
  80                         interrupts = < 8 >;
  81                 };
  82
  83                 /*
  84                  * According to DW Mobile Storage databook it is required
  85                  * to use  "Hold Register" if card is enumerated in SDR12 or
  86                  * SDR25 modes.
  87                  *
  88                  * Utilization of "Hold Register" is already implemented via
  89                  * dw_mci_pltfm_prepare_command() which in its turn gets
  90                  * used through dw_mci_drv_data->prepare_command call-back.
  91                  * This call-back is used in Altera Socfpga platform and so
  92                  * we may reuse it saying that we're compatible with their
  93                  * "altr,socfpga-dw-mshc".
  94                  *
  95                  * Most probably "Hold Register" utilization is platform-
  96                  * independent requirement which means that single unified
  97                  * "snps,dw-mshc" should be enough for all users of DW MMC once
  98                  * dw_mci_pltfm_prepare_command() is used in generic platform
  99                  * code.
 100                  */
 101                 mmc@0x15000 {
 102                         compatible = "altr,socfpga-dw-mshc";
 103                         reg = < 0x15000 0x400 >;
 104                         num-slots = < 1 >;
 105                         fifo-depth = < 16 >;
 106                         card-detect-delay = < 200 >;
 107                         clocks = <&apbclk>, <&mmcclk>;
 108                         clock-names = "biu", "ciu";
 109                         interrupts = < 7 >;
 110                         bus-width = < 4 >;
 111                 };
 112
 113                 uart@0x20000 {
 114                         compatible = "snps,dw-apb-uart";
 115                         reg = <0x20000 0x100>;
 116                         clock-frequency = <33333333>;
 117                         interrupts = <17>;
 118                         baud = <115200>;
 119                         reg-shift = <2>;
 120                         reg-io-width = <4>;
 121                 };
 122
 123                 uart@0x21000 {
 124                         compatible = "snps,dw-apb-uart";
 125                         reg = <0x21000 0x100>;
 126                         clock-frequency = <33333333>;
 127                         interrupts = <18>;
 128                         baud = <115200>;
 129                         reg-shift = <2>;
 130                         reg-io-width = <4>;
 131                 };
 132
 133                 /* UART muxed with USB data port (ttyS3) */
 134                 uart@0x22000 {
 135                         compatible = "snps,dw-apb-uart";
 136                         reg = <0x22000 0x100>;
 137                         clock-frequency = <33333333>;
 138                         interrupts = <19>;
 139                         baud = <115200>;
 140                         reg-shift = <2>;
 141                         reg-io-width = <4>;
 142                 };
 143
 144                 i2c@0x1d000 {
 145                         compatible = "snps,designware-i2c";
 146                         reg = <0x1d000 0x100>;
 147                         clock-frequency = <400000>;
 148                         clocks = <&i2cclk>;
 149                         interrupts = <14>;
 150                 };
 151
 152                 i2c@0x1e000 {
 153                         compatible = "snps,designware-i2c";
 154                         reg = <0x1e000 0x100>;
 155                         clock-frequency = <400000>;
 156                         clocks = <&i2cclk>;
 157                         interrupts = <15>;
 158                 };
 159
 160                 i2c@0x1f000 {
 161                         compatible = "snps,designware-i2c";
 162                         #address-cells = <1>;
 163                         #size-cells = <0>;
 164                         reg = <0x1f000 0x100>;
 165                         clock-frequency = <400000>;
 166                         clocks = <&i2cclk>;
 167                         interrupts = <16>;
 168
 169                         adv7511:adv7511@39{
 170                                 compatible="adi,adv7511";
 171                                 reg = <0x39>;
 172                                 interrupts = <23>;
 173                                 adi,input-depth = <8>;
 174                                 adi,input-colorspace = "rgb";
 175                                 adi,input-clock = "1x";
 176                                 adi,clock-delay = <0x03>;
 177
 178                                 ports {
 179                                         #address-cells = <1>;
 180                                         #size-cells = <0>;
 181
 182                                         /* RGB/YUV input */
 183                                         port@0 {
 184                                                 reg = <0>;
 185                                                 adv7511_input:endpoint {
 186                                                 remote-endpoint = <&pgu_output>;
 187                                                 };
 188                                         };
 189
 190                                         /* HDMI output */
 191                                         port@1 {
 192                                                 reg = <1>;
 193                                                 adv7511_output: endpoint {
 194                                                         remote-endpoint = <&hdmi_connector_in>;
 195                                                 };
 196                                         };
 197                                 };
 198                         };
 199
 200                         eeprom@0x54{
 201                                 compatible = "24c01";
 202                                 reg = <0x54>;
 203                                 pagesize = <0x8>;
 204                         };
 205
 206                         eeprom@0x57{
 207                                 compatible = "24c04";
 208                                 reg = <0x57>;
 209                                 pagesize = <0x8>;
 210                         };
 211                 };
 212
 213                 hdmi0: connector {
 214                         compatible = "hdmi-connector";
 215                         type = "a";
 216                         port {
 217                                 hdmi_connector_in: endpoint {
 218                                         remote-endpoint = <&adv7511_output>;
 219                                 };
 220                         };
 221                 };
 222
 223                 gpio0:gpio@13000 {
 224                         compatible = "snps,dw-apb-gpio";
 225                         reg = <0x13000 0x1000>;
 226                         #address-cells = <1>;
 227                         #size-cells = <0>;
 228
 229                         gpio0_banka: gpio-controller@0 {
 230                                 compatible = "snps,dw-apb-gpio-port";
 231                                 gpio-controller;
 232                                 #gpio-cells = <2>;
 233                                 snps,nr-gpios = <32>;
 234                                 reg = <0>;
 235                         };
 236
 237                         gpio0_bankb: gpio-controller@1 {
 238                                 compatible = "snps,dw-apb-gpio-port";
 239                                 gpio-controller;
 240                                 #gpio-cells = <2>;
 241                                 snps,nr-gpios = <8>;
 242                                 reg = <1>;
 243                         };
 244
 245                         gpio0_bankc: gpio-controller@2 {
 246                                 compatible = "snps,dw-apb-gpio-port";
 247                                 gpio-controller;
 248                                 #gpio-cells = <2>;
 249                                 snps,nr-gpios = <8>;
 250                                 reg = <2>;
 251                         };
 252                 };
 253
 254                 gpio1:gpio@14000 {
 255                         compatible = "snps,dw-apb-gpio";
 256                         reg = <0x14000 0x1000>;
 257                         #address-cells = <1>;
 258                         #size-cells = <0>;
 259
 260                         gpio1_banka: gpio-controller@0 {
 261                                 compatible = "snps,dw-apb-gpio-port";
 262                                 gpio-controller;
 263                                 #gpio-cells = <2>;
 264                                 snps,nr-gpios = <30>;
 265                                 reg = <0>;
 266                         };
 267
 268                         gpio1_bankb: gpio-controller@1 {
 269                                 compatible = "snps,dw-apb-gpio-port";
 270                                 gpio-controller;
 271                                 #gpio-cells = <2>;
 272                                 snps,nr-gpios = <10>;
 273                                 reg = <1>;
 274                         };
 275
 276                         gpio1_bankc: gpio-controller@2 {
 277                                 compatible = "snps,dw-apb-gpio-port";
 278                                 gpio-controller;
 279                                 #gpio-cells = <2>;
 280                                 snps,nr-gpios = <8>;
 281                                 reg = <2>;
 282                         };
 283                 };
 284
 285                 pgu@17000 {
 286                         compatible = "snps,arcpgu";
 287                         reg = <0x17000 0x400>;
 288                         encoder-slave = <&adv7511>;
 289                         clocks = <&pguclk>;
 290                         clock-names = "pxlclk";
 291                         memory-region = <&frame_buffer>;
 292                         port {
 293                                 pgu_output: endpoint {
 294                                         remote-endpoint = <&adv7511_input>;
 295                                 };
 296                         };
 297                 };
 298         };
 299 };