arch/arc/boot/dts/axs10x_mb.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Support for peripherals on the AXS10x mainboard
   4  *
   5  * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
   6  */
   7
   8 / {
   9         aliases {
  10                 ethernet = &gmac;
  11         };
  12
  13         axs10x_mb {
  14                 compatible = "simple-bus";
  15                 #address-cells = <1>;
  16                 #size-cells = <1>;
  17                 ranges = <0x00000000 0x0 0xe0000000 0x10000000>;
  18                 interrupt-parent = <&mb_intc>;
  19
  20                 creg_rst: reset-controller@11220 {
  21                         compatible = "snps,axs10x-reset";
  22                         #reset-cells = <1>;
  23                         reg = <0x11220 0x4>;
  24                 };
  25
  26                 i2sclk: i2sclk@100a0 {
  27                         compatible = "snps,axs10x-i2s-pll-clock";
  28                         reg = <0x100a0 0x10>;
  29                         clocks = <&i2spll_clk>;
  30                         #clock-cells = <0>;
  31                 };
  32
  33                 clocks {
  34                         i2spll_clk: i2spll_clk {
  35                                 compatible = "fixed-clock";
  36                                 clock-frequency = <27000000>;
  37                                 #clock-cells = <0>;
  38                         };
  39
  40                         i2cclk: i2cclk {
  41                                 compatible = "fixed-clock";
  42                                 clock-frequency = <50000000>;
  43                                 #clock-cells = <0>;
  44                         };
  45
  46                         apbclk: apbclk {
  47                                 compatible = "fixed-clock";
  48                                 clock-frequency = <50000000>;
  49                                 #clock-cells = <0>;
  50                         };
  51
  52                         mmcclk: mmcclk {
  53                                 compatible = "fixed-clock";
  54                                 /*
  55                                  * DW sdio controller has external ciu clock divider
  56                                  * controlled via register in SDIO IP. It divides
  57                                  * sdio_ref_clk (which comes from CGU) by 16 for
  58                                  * default. So default mmcclk clock (which comes
  59                                  * to sdk_in) is 25000000 Hz.
  60                                  */
  61                                 clock-frequency = <25000000>;
  62                                 #clock-cells = <0>;
  63                         };
  64                 };
  65
  66                 pguclk: pguclk@10080 {
  67                         compatible = "snps,axs10x-pgu-pll-clock";
  68                         reg = <0x10080 0x10>, <0x110 0x10>;
  69                         #clock-cells = <0>;
  70                         clocks = <&input_clk>;
  71                 };
  72
  73                 gmac: ethernet@18000 {
  74                         #interrupt-cells = <1>;
  75                         compatible = "snps,dwmac";
  76                         reg = < 0x18000 0x2000 >;
  77                         interrupts = < 4 >;
  78                         interrupt-names = "macirq";
  79                         phy-mode = "rgmii";
  80                         snps,pbl = < 32 >;
  81                         clocks = <&apbclk>;
  82                         clock-names = "stmmaceth";
  83                         max-speed = <100>;
  84                         resets = <&creg_rst 5>;
  85                         reset-names = "stmmaceth";
  86                         mac-address = [00 00 00 00 00 00]; /* Filled in by U-Boot */
  87                 };
  88
  89                 ehci@40000 {
  90                         compatible = "generic-ehci";
  91                         reg = < 0x40000 0x100 >;
  92                         interrupts = < 8 >;
  93                 };
  94
  95                 ohci@60000 {
  96                         compatible = "generic-ohci";
  97                         reg = < 0x60000 0x100 >;
  98                         interrupts = < 8 >;
  99                 };
 100
 101                 /*
 102                  * According to DW Mobile Storage databook it is required
 103                  * to use  "Hold Register" if card is enumerated in SDR12 or
 104                  * SDR25 modes.
 105                  *
 106                  * Utilization of "Hold Register" is already implemented via
 107                  * dw_mci_pltfm_prepare_command() which in its turn gets
 108                  * used through dw_mci_drv_data->prepare_command call-back.
 109                  * This call-back is used in Altera Socfpga platform and so
 110                  * we may reuse it saying that we're compatible with their
 111                  * "altr,socfpga-dw-mshc".
 112                  *
 113                  * Most probably "Hold Register" utilization is platform-
 114                  * independent requirement which means that single unified
 115                  * "snps,dw-mshc" should be enough for all users of DW MMC once
 116                  * dw_mci_pltfm_prepare_command() is used in generic platform
 117                  * code.
 118                  */
 119                 mmc@15000 {
 120                         compatible = "altr,socfpga-dw-mshc";
 121                         reg = < 0x15000 0x400 >;
 122                         fifo-depth = < 16 >;
 123                         card-detect-delay = < 200 >;
 124                         clocks = <&apbclk>, <&mmcclk>;
 125                         clock-names = "biu", "ciu";
 126                         interrupts = < 7 >;
 127                         bus-width = < 4 >;
 128                 };
 129
 130                 uart@20000 {
 131                         compatible = "snps,dw-apb-uart";
 132                         reg = <0x20000 0x100>;
 133                         clock-frequency = <33333333>;
 134                         interrupts = <17>;
 135                         baud = <115200>;
 136                         reg-shift = <2>;
 137                         reg-io-width = <4>;
 138                 };
 139
 140                 uart@21000 {
 141                         compatible = "snps,dw-apb-uart";
 142                         reg = <0x21000 0x100>;
 143                         clock-frequency = <33333333>;
 144                         interrupts = <18>;
 145                         baud = <115200>;
 146                         reg-shift = <2>;
 147                         reg-io-width = <4>;
 148                 };
 149
 150                 /* UART muxed with USB data port (ttyS3) */
 151                 uart@22000 {
 152                         compatible = "snps,dw-apb-uart";
 153                         reg = <0x22000 0x100>;
 154                         clock-frequency = <33333333>;
 155                         interrupts = <19>;
 156                         baud = <115200>;
 157                         reg-shift = <2>;
 158                         reg-io-width = <4>;
 159                 };
 160
 161                 i2c@1d000 {
 162                         compatible = "snps,designware-i2c";
 163                         reg = <0x1d000 0x100>;
 164                         clock-frequency = <400000>;
 165                         clocks = <&i2cclk>;
 166                         interrupts = <14>;
 167                 };
 168
 169                 i2s: i2s@1e000 {
 170                         compatible = "snps,designware-i2s";
 171                         reg = <0x1e000 0x100>;
 172                         clocks = <&i2sclk 0>;
 173                         clock-names = "i2sclk";
 174                         interrupts = <15>;
 175                         #sound-dai-cells = <0>;
 176                 };
 177
 178                 i2c@1f000 {
 179                         compatible = "snps,designware-i2c";
 180                         #address-cells = <1>;
 181                         #size-cells = <0>;
 182                         reg = <0x1f000 0x100>;
 183                         clock-frequency = <400000>;
 184                         clocks = <&i2cclk>;
 185                         interrupts = <16>;
 186
 187                         adv7511:adv7511@39{
 188                                 compatible="adi,adv7511";
 189                                 reg = <0x39>;
 190                                 interrupts = <23>;
 191                                 adi,input-depth = <8>;
 192                                 adi,input-colorspace = "rgb";
 193                                 adi,input-clock = "1x";
 194                                 adi,clock-delay = <0x03>;
 195                                 #sound-dai-cells = <0>;
 196
 197                                 ports {
 198                                         #address-cells = <1>;
 199                                         #size-cells = <0>;
 200
 201                                         /* RGB/YUV input */
 202                                         port@0 {
 203                                                 reg = <0>;
 204                                                 adv7511_input:endpoint {
 205                                                 remote-endpoint = <&pgu_output>;
 206                                                 };
 207                                         };
 208
 209                                         /* HDMI output */
 210                                         port@1 {
 211                                                 reg = <1>;
 212                                                 adv7511_output: endpoint {
 213                                                         remote-endpoint = <&hdmi_connector_in>;
 214                                                 };
 215                                         };
 216                                 };
 217                         };
 218
 219                         eeprom@54{
 220                                 compatible = "atmel,24c01";
 221                                 reg = <0x54>;
 222                                 pagesize = <0x8>;
 223                         };
 224
 225                         eeprom@57{
 226                                 compatible = "atmel,24c04";
 227                                 reg = <0x57>;
 228                                 pagesize = <0x8>;
 229                         };
 230                 };
 231
 232                 hdmi0: connector {
 233                         compatible = "hdmi-connector";
 234                         type = "a";
 235                         port {
 236                                 hdmi_connector_in: endpoint {
 237                                         remote-endpoint = <&adv7511_output>;
 238                                 };
 239                         };
 240                 };
 241
 242                 gpio0:gpio@13000 {
 243                         compatible = "snps,dw-apb-gpio";
 244                         reg = <0x13000 0x1000>;
 245                         #address-cells = <1>;
 246                         #size-cells = <0>;
 247
 248                         gpio0_banka: gpio-controller@0 {
 249                                 compatible = "snps,dw-apb-gpio-port";
 250                                 gpio-controller;
 251                                 #gpio-cells = <2>;
 252                                 snps,nr-gpios = <32>;
 253                                 reg = <0>;
 254                         };
 255
 256                         gpio0_bankb: gpio-controller@1 {
 257                                 compatible = "snps,dw-apb-gpio-port";
 258                                 gpio-controller;
 259                                 #gpio-cells = <2>;
 260                                 snps,nr-gpios = <8>;
 261                                 reg = <1>;
 262                         };
 263
 264                         gpio0_bankc: gpio-controller@2 {
 265                                 compatible = "snps,dw-apb-gpio-port";
 266                                 gpio-controller;
 267                                 #gpio-cells = <2>;
 268                                 snps,nr-gpios = <8>;
 269                                 reg = <2>;
 270                         };
 271                 };
 272
 273                 gpio1:gpio@14000 {
 274                         compatible = "snps,dw-apb-gpio";
 275                         reg = <0x14000 0x1000>;
 276                         #address-cells = <1>;
 277                         #size-cells = <0>;
 278
 279                         gpio1_banka: gpio-controller@0 {
 280                                 compatible = "snps,dw-apb-gpio-port";
 281                                 gpio-controller;
 282                                 #gpio-cells = <2>;
 283                                 snps,nr-gpios = <30>;
 284                                 reg = <0>;
 285                         };
 286
 287                         gpio1_bankb: gpio-controller@1 {
 288                                 compatible = "snps,dw-apb-gpio-port";
 289                                 gpio-controller;
 290                                 #gpio-cells = <2>;
 291                                 snps,nr-gpios = <10>;
 292                                 reg = <1>;
 293                         };
 294
 295                         gpio1_bankc: gpio-controller@2 {
 296                                 compatible = "snps,dw-apb-gpio-port";
 297                                 gpio-controller;
 298                                 #gpio-cells = <2>;
 299                                 snps,nr-gpios = <8>;
 300                                 reg = <2>;
 301                         };
 302                 };
 303
 304                 pgu@17000 {
 305                         compatible = "snps,arcpgu";
 306                         reg = <0x17000 0x400>;
 307                         encoder-slave = <&adv7511>;
 308                         clocks = <&pguclk>;
 309                         clock-names = "pxlclk";
 310                         memory-region = <&frame_buffer>;
 311                         port {
 312                                 pgu_output: endpoint {
 313                                         remote-endpoint = <&adv7511_input>;
 314                                 };
 315                         };
 316                 };
 317
 318                 sound_playback {
 319                         compatible = "simple-audio-card";
 320                         simple-audio-card,name = "AXS10x HDMI Audio";
 321                         simple-audio-card,format = "i2s";
 322                         simple-audio-card,cpu {
 323                                 sound-dai = <&i2s>;
 324                         };
 325                         simple-audio-card,codec {
 326                                 sound-dai = <&adv7511>;
 327                         };
 328                 };
 329         };
 330 };