arch/arc/boot/dts/axs10x_mb.dtsi

   1 /*
   2  * Support for peripherals on the AXS10x mainboard
   3  *
   4  * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 / {
  12         axs10x_mb {
  13                 compatible = "simple-bus";
  14                 #address-cells = <1>;
  15                 #size-cells = <1>;
  16                 ranges = <0x00000000 0x0 0xe0000000 0x10000000>;
  17                 interrupt-parent = <&mb_intc>;
  18
  19                 i2sclk: i2sclk@100a0 {
  20                         compatible = "snps,axs10x-i2s-pll-clock";
  21                         reg = <0x100a0 0x10>;
  22                         clocks = <&i2spll_clk>;
  23                         #clock-cells = <0>;
  24                 };
  25
  26                 clocks {
  27                         i2spll_clk: i2spll_clk {
  28                                 compatible = "fixed-clock";
  29                                 clock-frequency = <27000000>;
  30                                 #clock-cells = <0>;
  31                         };
  32
  33                         i2cclk: i2cclk {
  34                                 compatible = "fixed-clock";
  35                                 clock-frequency = <50000000>;
  36                                 #clock-cells = <0>;
  37                         };
  38
  39                         apbclk: apbclk {
  40                                 compatible = "fixed-clock";
  41                                 clock-frequency = <50000000>;
  42                                 #clock-cells = <0>;
  43                         };
  44
  45                         mmcclk: mmcclk {
  46                                 compatible = "fixed-clock";
  47                                 /*
  48                                  * DW sdio controller has external ciu clock divider
  49                                  * controlled via register in SDIO IP. It divides
  50                                  * sdio_ref_clk (which comes from CGU) by 16 for
  51                                  * default. So default mmcclk clock (which comes
  52                                  * to sdk_in) is 25000000 Hz.
  53                                  */
  54                                 clock-frequency = <25000000>;
  55                                 #clock-cells = <0>;
  56                         };
  57
  58                         pguclk: pguclk {
  59                                 #clock-cells = <0>;
  60                                 compatible = "fixed-clock";
  61                                 clock-frequency = <74250000>;
  62                         };
  63                 };
  64
  65                 ethernet@0x18000 {
  66                         #interrupt-cells = <1>;
  67                         compatible = "snps,dwmac";
  68                         reg = < 0x18000 0x2000 >;
  69                         interrupts = < 4 >;
  70                         interrupt-names = "macirq";
  71                         phy-mode = "rgmii";
  72                         snps,pbl = < 32 >;
  73                         clocks = <&apbclk>;
  74                         clock-names = "stmmaceth";
  75                         max-speed = <100>;
  76                 };
  77
  78                 ehci@0x40000 {
  79                         compatible = "generic-ehci";
  80                         reg = < 0x40000 0x100 >;
  81                         interrupts = < 8 >;
  82                 };
  83
  84                 ohci@0x60000 {
  85                         compatible = "generic-ohci";
  86                         reg = < 0x60000 0x100 >;
  87                         interrupts = < 8 >;
  88                 };
  89
  90                 /*
  91                  * According to DW Mobile Storage databook it is required
  92                  * to use  "Hold Register" if card is enumerated in SDR12 or
  93                  * SDR25 modes.
  94                  *
  95                  * Utilization of "Hold Register" is already implemented via
  96                  * dw_mci_pltfm_prepare_command() which in its turn gets
  97                  * used through dw_mci_drv_data->prepare_command call-back.
  98                  * This call-back is used in Altera Socfpga platform and so
  99                  * we may reuse it saying that we're compatible with their
 100                  * "altr,socfpga-dw-mshc".
 101                  *
 102                  * Most probably "Hold Register" utilization is platform-
 103                  * independent requirement which means that single unified
 104                  * "snps,dw-mshc" should be enough for all users of DW MMC once
 105                  * dw_mci_pltfm_prepare_command() is used in generic platform
 106                  * code.
 107                  */
 108                 mmc@0x15000 {
 109                         compatible = "altr,socfpga-dw-mshc";
 110                         reg = < 0x15000 0x400 >;
 111                         fifo-depth = < 16 >;
 112                         card-detect-delay = < 200 >;
 113                         clocks = <&apbclk>, <&mmcclk>;
 114                         clock-names = "biu", "ciu";
 115                         interrupts = < 7 >;
 116                         bus-width = < 4 >;
 117                 };
 118
 119                 uart@0x20000 {
 120                         compatible = "snps,dw-apb-uart";
 121                         reg = <0x20000 0x100>;
 122                         clock-frequency = <33333333>;
 123                         interrupts = <17>;
 124                         baud = <115200>;
 125                         reg-shift = <2>;
 126                         reg-io-width = <4>;
 127                 };
 128
 129                 uart@0x21000 {
 130                         compatible = "snps,dw-apb-uart";
 131                         reg = <0x21000 0x100>;
 132                         clock-frequency = <33333333>;
 133                         interrupts = <18>;
 134                         baud = <115200>;
 135                         reg-shift = <2>;
 136                         reg-io-width = <4>;
 137                 };
 138
 139                 /* UART muxed with USB data port (ttyS3) */
 140                 uart@0x22000 {
 141                         compatible = "snps,dw-apb-uart";
 142                         reg = <0x22000 0x100>;
 143                         clock-frequency = <33333333>;
 144                         interrupts = <19>;
 145                         baud = <115200>;
 146                         reg-shift = <2>;
 147                         reg-io-width = <4>;
 148                 };
 149
 150                 i2c@0x1d000 {
 151                         compatible = "snps,designware-i2c";
 152                         reg = <0x1d000 0x100>;
 153                         clock-frequency = <400000>;
 154                         clocks = <&i2cclk>;
 155                         interrupts = <14>;
 156                 };
 157
 158                 i2s: i2s@1e000 {
 159                         compatible = "snps,designware-i2s";
 160                         reg = <0x1e000 0x100>;
 161                         clocks = <&i2sclk 0>;
 162                         clock-names = "i2sclk";
 163                         interrupts = <15>;
 164                         #sound-dai-cells = <0>;
 165                 };
 166
 167                 i2c@0x1f000 {
 168                         compatible = "snps,designware-i2c";
 169                         #address-cells = <1>;
 170                         #size-cells = <0>;
 171                         reg = <0x1f000 0x100>;
 172                         clock-frequency = <400000>;
 173                         clocks = <&i2cclk>;
 174                         interrupts = <16>;
 175
 176                         adv7511:adv7511@39{
 177                                 compatible="adi,adv7511";
 178                                 reg = <0x39>;
 179                                 interrupts = <23>;
 180                                 adi,input-depth = <8>;
 181                                 adi,input-colorspace = "rgb";
 182                                 adi,input-clock = "1x";
 183                                 adi,clock-delay = <0x03>;
 184                                 #sound-dai-cells = <0>;
 185
 186                                 ports {
 187                                         #address-cells = <1>;
 188                                         #size-cells = <0>;
 189
 190                                         /* RGB/YUV input */
 191                                         port@0 {
 192                                                 reg = <0>;
 193                                                 adv7511_input:endpoint {
 194                                                 remote-endpoint = <&pgu_output>;
 195                                                 };
 196                                         };
 197
 198                                         /* HDMI output */
 199                                         port@1 {
 200                                                 reg = <1>;
 201                                                 adv7511_output: endpoint {
 202                                                         remote-endpoint = <&hdmi_connector_in>;
 203                                                 };
 204                                         };
 205                                 };
 206                         };
 207
 208                         eeprom@0x54{
 209                                 compatible = "24c01";
 210                                 reg = <0x54>;
 211                                 pagesize = <0x8>;
 212                         };
 213
 214                         eeprom@0x57{
 215                                 compatible = "24c04";
 216                                 reg = <0x57>;
 217                                 pagesize = <0x8>;
 218                         };
 219                 };
 220
 221                 hdmi0: connector {
 222                         compatible = "hdmi-connector";
 223                         type = "a";
 224                         port {
 225                                 hdmi_connector_in: endpoint {
 226                                         remote-endpoint = <&adv7511_output>;
 227                                 };
 228                         };
 229                 };
 230
 231                 gpio0:gpio@13000 {
 232                         compatible = "snps,dw-apb-gpio";
 233                         reg = <0x13000 0x1000>;
 234                         #address-cells = <1>;
 235                         #size-cells = <0>;
 236
 237                         gpio0_banka: gpio-controller@0 {
 238                                 compatible = "snps,dw-apb-gpio-port";
 239                                 gpio-controller;
 240                                 #gpio-cells = <2>;
 241                                 snps,nr-gpios = <32>;
 242                                 reg = <0>;
 243                         };
 244
 245                         gpio0_bankb: gpio-controller@1 {
 246                                 compatible = "snps,dw-apb-gpio-port";
 247                                 gpio-controller;
 248                                 #gpio-cells = <2>;
 249                                 snps,nr-gpios = <8>;
 250                                 reg = <1>;
 251                         };
 252
 253                         gpio0_bankc: gpio-controller@2 {
 254                                 compatible = "snps,dw-apb-gpio-port";
 255                                 gpio-controller;
 256                                 #gpio-cells = <2>;
 257                                 snps,nr-gpios = <8>;
 258                                 reg = <2>;
 259                         };
 260                 };
 261
 262                 gpio1:gpio@14000 {
 263                         compatible = "snps,dw-apb-gpio";
 264                         reg = <0x14000 0x1000>;
 265                         #address-cells = <1>;
 266                         #size-cells = <0>;
 267
 268                         gpio1_banka: gpio-controller@0 {
 269                                 compatible = "snps,dw-apb-gpio-port";
 270                                 gpio-controller;
 271                                 #gpio-cells = <2>;
 272                                 snps,nr-gpios = <30>;
 273                                 reg = <0>;
 274                         };
 275
 276                         gpio1_bankb: gpio-controller@1 {
 277                                 compatible = "snps,dw-apb-gpio-port";
 278                                 gpio-controller;
 279                                 #gpio-cells = <2>;
 280                                 snps,nr-gpios = <10>;
 281                                 reg = <1>;
 282                         };
 283
 284                         gpio1_bankc: gpio-controller@2 {
 285                                 compatible = "snps,dw-apb-gpio-port";
 286                                 gpio-controller;
 287                                 #gpio-cells = <2>;
 288                                 snps,nr-gpios = <8>;
 289                                 reg = <2>;
 290                         };
 291                 };
 292
 293                 pgu@17000 {
 294                         compatible = "snps,arcpgu";
 295                         reg = <0x17000 0x400>;
 296                         encoder-slave = <&adv7511>;
 297                         clocks = <&pguclk>;
 298                         clock-names = "pxlclk";
 299                         memory-region = <&frame_buffer>;
 300                         port {
 301                                 pgu_output: endpoint {
 302                                         remote-endpoint = <&adv7511_input>;
 303                                 };
 304                         };
 305                 };
 306
 307                 sound_playback {
 308                         compatible = "simple-audio-card";
 309                         simple-audio-card,name = "AXS10x HDMI Audio";
 310                         simple-audio-card,format = "i2s";
 311                         simple-audio-card,cpu {
 312                                 sound-dai = <&i2s>;
 313                         };
 314                         simple-audio-card,codec {
 315                                 sound-dai = <&adv7511>;
 316                         };
 317                 };
 318         };
 319 };