arch/arc/boot/dts/axs10x_mb.dtsi

   1 /*
   2  * Support for peripherals on the AXS10x mainboard
   3  *
   4  * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 / {
  12         axs10x_mb {
  13                 compatible = "simple-bus";
  14                 #address-cells = <1>;
  15                 #size-cells = <1>;
  16                 ranges = <0x00000000 0x0 0xe0000000 0x10000000>;
  17                 interrupt-parent = <&mb_intc>;
  18
  19                 creg_rst: reset-controller@11220 {
  20                         compatible = "snps,axs10x-reset";
  21                         #reset-cells = <1>;
  22                         reg = <0x11220 0x4>;
  23                 };
  24
  25                 i2sclk: i2sclk@100a0 {
  26                         compatible = "snps,axs10x-i2s-pll-clock";
  27                         reg = <0x100a0 0x10>;
  28                         clocks = <&i2spll_clk>;
  29                         #clock-cells = <0>;
  30                 };
  31
  32                 clocks {
  33                         i2spll_clk: i2spll_clk {
  34                                 compatible = "fixed-clock";
  35                                 clock-frequency = <27000000>;
  36                                 #clock-cells = <0>;
  37                         };
  38
  39                         i2cclk: i2cclk {
  40                                 compatible = "fixed-clock";
  41                                 clock-frequency = <50000000>;
  42                                 #clock-cells = <0>;
  43                         };
  44
  45                         apbclk: apbclk {
  46                                 compatible = "fixed-clock";
  47                                 clock-frequency = <50000000>;
  48                                 #clock-cells = <0>;
  49                         };
  50
  51                         mmcclk: mmcclk {
  52                                 compatible = "fixed-clock";
  53                                 /*
  54                                  * DW sdio controller has external ciu clock divider
  55                                  * controlled via register in SDIO IP. It divides
  56                                  * sdio_ref_clk (which comes from CGU) by 16 for
  57                                  * default. So default mmcclk clock (which comes
  58                                  * to sdk_in) is 25000000 Hz.
  59                                  */
  60                                 clock-frequency = <25000000>;
  61                                 #clock-cells = <0>;
  62                         };
  63
  64                         pguclk: pguclk {
  65                                 #clock-cells = <0>;
  66                                 compatible = "fixed-clock";
  67                                 clock-frequency = <74250000>;
  68                         };
  69                 };
  70
  71                 ethernet@0x18000 {
  72                         #interrupt-cells = <1>;
  73                         compatible = "snps,dwmac";
  74                         reg = < 0x18000 0x2000 >;
  75                         interrupts = < 4 >;
  76                         interrupt-names = "macirq";
  77                         phy-mode = "rgmii";
  78                         snps,pbl = < 32 >;
  79                         clocks = <&apbclk>;
  80                         clock-names = "stmmaceth";
  81                         max-speed = <100>;
  82                         resets = <&creg_rst 5>;
  83                         reset-names = "stmmaceth";
  84                 };
  85
  86                 ehci@0x40000 {
  87                         compatible = "generic-ehci";
  88                         reg = < 0x40000 0x100 >;
  89                         interrupts = < 8 >;
  90                 };
  91
  92                 ohci@0x60000 {
  93                         compatible = "generic-ohci";
  94                         reg = < 0x60000 0x100 >;
  95                         interrupts = < 8 >;
  96                 };
  97
  98                 /*
  99                  * According to DW Mobile Storage databook it is required
 100                  * to use  "Hold Register" if card is enumerated in SDR12 or
 101                  * SDR25 modes.
 102                  *
 103                  * Utilization of "Hold Register" is already implemented via
 104                  * dw_mci_pltfm_prepare_command() which in its turn gets
 105                  * used through dw_mci_drv_data->prepare_command call-back.
 106                  * This call-back is used in Altera Socfpga platform and so
 107                  * we may reuse it saying that we're compatible with their
 108                  * "altr,socfpga-dw-mshc".
 109                  *
 110                  * Most probably "Hold Register" utilization is platform-
 111                  * independent requirement which means that single unified
 112                  * "snps,dw-mshc" should be enough for all users of DW MMC once
 113                  * dw_mci_pltfm_prepare_command() is used in generic platform
 114                  * code.
 115                  */
 116                 mmc@0x15000 {
 117                         compatible = "altr,socfpga-dw-mshc";
 118                         reg = < 0x15000 0x400 >;
 119                         fifo-depth = < 16 >;
 120                         card-detect-delay = < 200 >;
 121                         clocks = <&apbclk>, <&mmcclk>;
 122                         clock-names = "biu", "ciu";
 123                         interrupts = < 7 >;
 124                         bus-width = < 4 >;
 125                 };
 126
 127                 uart@0x20000 {
 128                         compatible = "snps,dw-apb-uart";
 129                         reg = <0x20000 0x100>;
 130                         clock-frequency = <33333333>;
 131                         interrupts = <17>;
 132                         baud = <115200>;
 133                         reg-shift = <2>;
 134                         reg-io-width = <4>;
 135                 };
 136
 137                 uart@0x21000 {
 138                         compatible = "snps,dw-apb-uart";
 139                         reg = <0x21000 0x100>;
 140                         clock-frequency = <33333333>;
 141                         interrupts = <18>;
 142                         baud = <115200>;
 143                         reg-shift = <2>;
 144                         reg-io-width = <4>;
 145                 };
 146
 147                 /* UART muxed with USB data port (ttyS3) */
 148                 uart@0x22000 {
 149                         compatible = "snps,dw-apb-uart";
 150                         reg = <0x22000 0x100>;
 151                         clock-frequency = <33333333>;
 152                         interrupts = <19>;
 153                         baud = <115200>;
 154                         reg-shift = <2>;
 155                         reg-io-width = <4>;
 156                 };
 157
 158                 i2c@0x1d000 {
 159                         compatible = "snps,designware-i2c";
 160                         reg = <0x1d000 0x100>;
 161                         clock-frequency = <400000>;
 162                         clocks = <&i2cclk>;
 163                         interrupts = <14>;
 164                 };
 165
 166                 i2s: i2s@1e000 {
 167                         compatible = "snps,designware-i2s";
 168                         reg = <0x1e000 0x100>;
 169                         clocks = <&i2sclk 0>;
 170                         clock-names = "i2sclk";
 171                         interrupts = <15>;
 172                         #sound-dai-cells = <0>;
 173                 };
 174
 175                 i2c@0x1f000 {
 176                         compatible = "snps,designware-i2c";
 177                         #address-cells = <1>;
 178                         #size-cells = <0>;
 179                         reg = <0x1f000 0x100>;
 180                         clock-frequency = <400000>;
 181                         clocks = <&i2cclk>;
 182                         interrupts = <16>;
 183
 184                         adv7511:adv7511@39{
 185                                 compatible="adi,adv7511";
 186                                 reg = <0x39>;
 187                                 interrupts = <23>;
 188                                 adi,input-depth = <8>;
 189                                 adi,input-colorspace = "rgb";
 190                                 adi,input-clock = "1x";
 191                                 adi,clock-delay = <0x03>;
 192                                 #sound-dai-cells = <0>;
 193
 194                                 ports {
 195                                         #address-cells = <1>;
 196                                         #size-cells = <0>;
 197
 198                                         /* RGB/YUV input */
 199                                         port@0 {
 200                                                 reg = <0>;
 201                                                 adv7511_input:endpoint {
 202                                                 remote-endpoint = <&pgu_output>;
 203                                                 };
 204                                         };
 205
 206                                         /* HDMI output */
 207                                         port@1 {
 208                                                 reg = <1>;
 209                                                 adv7511_output: endpoint {
 210                                                         remote-endpoint = <&hdmi_connector_in>;
 211                                                 };
 212                                         };
 213                                 };
 214                         };
 215
 216                         eeprom@0x54{
 217                                 compatible = "24c01";
 218                                 reg = <0x54>;
 219                                 pagesize = <0x8>;
 220                         };
 221
 222                         eeprom@0x57{
 223                                 compatible = "24c04";
 224                                 reg = <0x57>;
 225                                 pagesize = <0x8>;
 226                         };
 227                 };
 228
 229                 hdmi0: connector {
 230                         compatible = "hdmi-connector";
 231                         type = "a";
 232                         port {
 233                                 hdmi_connector_in: endpoint {
 234                                         remote-endpoint = <&adv7511_output>;
 235                                 };
 236                         };
 237                 };
 238
 239                 gpio0:gpio@13000 {
 240                         compatible = "snps,dw-apb-gpio";
 241                         reg = <0x13000 0x1000>;
 242                         #address-cells = <1>;
 243                         #size-cells = <0>;
 244
 245                         gpio0_banka: gpio-controller@0 {
 246                                 compatible = "snps,dw-apb-gpio-port";
 247                                 gpio-controller;
 248                                 #gpio-cells = <2>;
 249                                 snps,nr-gpios = <32>;
 250                                 reg = <0>;
 251                         };
 252
 253                         gpio0_bankb: gpio-controller@1 {
 254                                 compatible = "snps,dw-apb-gpio-port";
 255                                 gpio-controller;
 256                                 #gpio-cells = <2>;
 257                                 snps,nr-gpios = <8>;
 258                                 reg = <1>;
 259                         };
 260
 261                         gpio0_bankc: gpio-controller@2 {
 262                                 compatible = "snps,dw-apb-gpio-port";
 263                                 gpio-controller;
 264                                 #gpio-cells = <2>;
 265                                 snps,nr-gpios = <8>;
 266                                 reg = <2>;
 267                         };
 268                 };
 269
 270                 gpio1:gpio@14000 {
 271                         compatible = "snps,dw-apb-gpio";
 272                         reg = <0x14000 0x1000>;
 273                         #address-cells = <1>;
 274                         #size-cells = <0>;
 275
 276                         gpio1_banka: gpio-controller@0 {
 277                                 compatible = "snps,dw-apb-gpio-port";
 278                                 gpio-controller;
 279                                 #gpio-cells = <2>;
 280                                 snps,nr-gpios = <30>;
 281                                 reg = <0>;
 282                         };
 283
 284                         gpio1_bankb: gpio-controller@1 {
 285                                 compatible = "snps,dw-apb-gpio-port";
 286                                 gpio-controller;
 287                                 #gpio-cells = <2>;
 288                                 snps,nr-gpios = <10>;
 289                                 reg = <1>;
 290                         };
 291
 292                         gpio1_bankc: gpio-controller@2 {
 293                                 compatible = "snps,dw-apb-gpio-port";
 294                                 gpio-controller;
 295                                 #gpio-cells = <2>;
 296                                 snps,nr-gpios = <8>;
 297                                 reg = <2>;
 298                         };
 299                 };
 300
 301                 pgu@17000 {
 302                         compatible = "snps,arcpgu";
 303                         reg = <0x17000 0x400>;
 304                         encoder-slave = <&adv7511>;
 305                         clocks = <&pguclk>;
 306                         clock-names = "pxlclk";
 307                         memory-region = <&frame_buffer>;
 308                         port {
 309                                 pgu_output: endpoint {
 310                                         remote-endpoint = <&adv7511_input>;
 311                                 };
 312                         };
 313                 };
 314
 315                 sound_playback {
 316                         compatible = "simple-audio-card";
 317                         simple-audio-card,name = "AXS10x HDMI Audio";
 318                         simple-audio-card,format = "i2s";
 319                         simple-audio-card,cpu {
 320                                 sound-dai = <&i2s>;
 321                         };
 322                         simple-audio-card,codec {
 323                                 sound-dai = <&adv7511>;
 324                         };
 325                 };
 326         };
 327 };