arch/arc/boot/dts/axc003_idu.dtsi

   1 /*
   2  * Copyright (C) 2014, 2015 Synopsys, Inc. (www.synopsys.com)
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 /*
  10  * Device tree for AXC003 CPU card: HS38x2 (Dual Core) with IDU intc
  11  */
  12
  13 /include/ "skeleton_hs_idu.dtsi"
  14
  15 / {
  16         compatible = "snps,arc";
  17         #address-cells = <2>;
  18         #size-cells = <2>;
  19
  20         cpu_card {
  21                 compatible = "simple-bus";
  22                 #address-cells = <1>;
  23                 #size-cells = <1>;
  24
  25                 ranges = <0x00000000 0x0 0xf0000000 0x10000000>;
  26
  27                 input_clk: input-clk {
  28                         #clock-cells = <0>;
  29                         compatible = "fixed-clock";
  30                         clock-frequency = <33333333>;
  31                 };
  32
  33                 core_clk: core-clk@80 {
  34                         compatible = "snps,axs10x-arc-pll-clock";
  35                         reg = <0x80 0x10>, <0x100 0x10>;
  36                         #clock-cells = <0>;
  37                         clocks = <&input_clk>;
  38
  39                         /*
  40                          * Set initial core pll output frequency to 100MHz.
  41                          * It will be applied at the core pll driver probing
  42                          * on early boot.
  43                          */
  44                         assigned-clocks = <&core_clk>;
  45                         assigned-clock-rates = <100000000>;
  46                 };
  47
  48                 core_intc: archs-intc@cpu {
  49                         compatible = "snps,archs-intc";
  50                         interrupt-controller;
  51                         #interrupt-cells = <1>;
  52                 };
  53
  54                 idu_intc: idu-interrupt-controller {
  55                         compatible = "snps,archs-idu-intc";
  56                         interrupt-controller;
  57                         interrupt-parent = <&core_intc>;
  58                         #interrupt-cells = <1>;
  59                 };
  60
  61                 /*
  62                  * this GPIO block ORs all interrupts on CPU card (creg,..)
  63                  * to uplink only 1 IRQ to ARC core intc
  64                  */
  65                 dw-apb-gpio@2000 {
  66                         compatible = "snps,dw-apb-gpio";
  67                         reg = < 0x2000 0x80 >;
  68                         #address-cells = <1>;
  69                         #size-cells = <0>;
  70
  71                         ictl_intc: gpio-controller@0 {
  72                                 compatible = "snps,dw-apb-gpio-port";
  73                                 gpio-controller;
  74                                 #gpio-cells = <2>;
  75                                 snps,nr-gpios = <30>;
  76                                 reg = <0>;
  77                                 interrupt-controller;
  78                                 #interrupt-cells = <2>;
  79                                 interrupt-parent = <&idu_intc>;
  80                                 interrupts = <1>;
  81                         };
  82                 };
  83
  84                 debug_uart: dw-apb-uart@5000 {
  85                         compatible = "snps,dw-apb-uart";
  86                         reg = <0x5000 0x100>;
  87                         clock-frequency = <33333000>;
  88                         interrupt-parent = <&ictl_intc>;
  89                         interrupts = <2 4>;
  90                         baud = <115200>;
  91                         reg-shift = <2>;
  92                         reg-io-width = <4>;
  93                 };
  94
  95                 arcpct0: pct {
  96                         compatible = "snps,archs-pct";
  97                         #interrupt-cells = <1>;
  98                         interrupt-parent = <&core_intc>;
  99                         interrupts = <20>;
 100                 };
 101         };
 102
 103         /*
 104          * Mark DMA peripherals connected via IOC port as dma-coherent. We do
 105          * it via overlay because peripherals defined in axs10x_mb.dtsi are
 106          * used for both AXS101 and AXS103 boards and only AXS103 has IOC (so
 107          * only AXS103 board has HW-coherent DMA peripherals)
 108          * We don't need to mark pgu@17000 as dma-coherent because it uses
 109          * external DMA buffer located outside of IOC aperture.
 110          */
 111         axs10x_mb {
 112                 ethernet@18000 {
 113                         dma-coherent;
 114                 };
 115
 116                 ehci@40000 {
 117                         dma-coherent;
 118                 };
 119
 120                 ohci@60000 {
 121                         dma-coherent;
 122                 };
 123
 124                 mmc@15000 {
 125                         dma-coherent;
 126                 };
 127         };
 128
 129         /*
 130          * This INTC is actually connected to DW APB GPIO
 131          * which acts as a wire between MB INTC and CPU INTC.
 132          * GPIO INTC is configured in platform init code
 133          * and here we mimic direct connection from MB INTC to
 134          * CPU INTC, thus we set "interrupts = <0 1>" instead of
 135          * "interrupts = <12>"
 136          *
 137          * This intc actually resides on MB, but we move it here to
 138          * avoid duplicating the MB dtsi file given that IRQ from
 139          * this intc to cpu intc are different for axs101 and axs103
 140          */
 141         mb_intc: dw-apb-ictl@e0012000 {
 142                 #interrupt-cells = <1>;
 143                 compatible = "snps,dw-apb-ictl";
 144                 reg = < 0x0 0xe0012000 0x0 0x200 >;
 145                 interrupt-controller;
 146                 interrupt-parent = <&idu_intc>;
 147                 interrupts = <0>;
 148         };
 149
 150         memory {
 151                 device_type = "memory";
 152                 /* CONFIG_LINUX_RAM_BASE needs to match low mem start */
 153                 reg = <0x0 0x80000000 0x0 0x20000000    /* 512 MiB low mem */
 154                        0x1 0xc0000000 0x0 0x40000000>;  /* 1 GiB highmem */
 155         };
 156
 157         reserved-memory {
 158                 #address-cells = <2>;
 159                 #size-cells = <2>;
 160                 ranges;
 161                 /*
 162                  * Move frame buffer out of IOC aperture (0x8z-0xaz).
 163                  */
 164                 frame_buffer: frame_buffer@be000000 {
 165                         compatible = "shared-dma-pool";
 166                         reg = <0x0 0xbe000000 0x0 0x2000000>;
 167                         no-map;
 168                 };
 169         };
 170 };