arch/arc/boot/dts/axc003.dtsi

   1 /*
   2  * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 /*
  10  * Device tree for AXC003 CPU card: HS38x UP configuration
  11  */
  12
  13 /include/ "skeleton_hs.dtsi"
  14
  15 / {
  16         compatible = "snps,arc";
  17         clock-frequency = <90000000>;
  18         #address-cells = <1>;
  19         #size-cells = <1>;
  20
  21         cpu_card {
  22                 compatible = "simple-bus";
  23                 #address-cells = <1>;
  24                 #size-cells = <1>;
  25
  26                 ranges = <0x00000000 0xf0000000 0x10000000>;
  27
  28                 core_clk: core_clk {
  29                         #clock-cells = <0>;
  30                         compatible = "fixed-clock";
  31                         clock-frequency = <90000000>;
  32                 };
  33
  34                 core_intc: archs-intc@cpu {
  35                         compatible = "snps,archs-intc";
  36                         interrupt-controller;
  37                         #interrupt-cells = <1>;
  38                 };
  39
  40                 /*
  41                  * this GPIO block ORs all interrupts on CPU card (creg,..)
  42                  * to uplink only 1 IRQ to ARC core intc
  43                  */
  44                 dw-apb-gpio@0x2000 {
  45                         compatible = "snps,dw-apb-gpio";
  46                         reg = < 0x2000 0x80 >;
  47                         #address-cells = <1>;
  48                         #size-cells = <0>;
  49
  50                         ictl_intc: gpio-controller@0 {
  51                                 compatible = "snps,dw-apb-gpio-port";
  52                                 gpio-controller;
  53                                 #gpio-cells = <2>;
  54                                 snps,nr-gpios = <30>;
  55                                 reg = <0>;
  56                                 interrupt-controller;
  57                                 #interrupt-cells = <2>;
  58                                 interrupt-parent = <&core_intc>;
  59                                 interrupts = <25>;
  60                         };
  61                 };
  62
  63                 debug_uart: dw-apb-uart@0x5000 {
  64                         compatible = "snps,dw-apb-uart";
  65                         reg = <0x5000 0x100>;
  66                         clock-frequency = <33333000>;
  67                         interrupt-parent = <&ictl_intc>;
  68                         interrupts = <2 4>;
  69                         baud = <115200>;
  70                         reg-shift = <2>;
  71                         reg-io-width = <4>;
  72                 };
  73
  74                 arcpct0: pct {
  75                         compatible = "snps,archs-pct";
  76                         #interrupt-cells = <1>;
  77                         interrupt-parent = <&core_intc>;
  78                         interrupts = <20>;
  79                 };
  80         };
  81
  82         /*
  83          * The DW APB ICTL intc on MB is connected to CPU intc via a
  84          * DT "invisible" DW APB GPIO block, configured to simply pass thru
  85          * interrupts - setup accordinly in platform init (plat-axs10x/ax10x.c)
  86          *
  87          * So here we mimic a direct connection betwen them, ignoring the
  88          * ABPG GPIO. Thus set "interrupts = <24>" (DW APB GPIO to core)
  89          * instead of "interrupts = <12>" (DW APB ICTL to DW APB GPIO)
  90          *
  91          * This intc actually resides on MB, but we move it here to
  92          * avoid duplicating the MB dtsi file given that IRQ from
  93          * this intc to cpu intc are different for axs101 and axs103
  94          */
  95         mb_intc: dw-apb-ictl@0xe0012000 {
  96                 #interrupt-cells = <1>;
  97                 compatible = "snps,dw-apb-ictl";
  98                 reg = < 0xe0012000 0x200 >;
  99                 interrupt-controller;
 100                 interrupt-parent = <&core_intc>;
 101                 interrupts = < 24 >;
 102         };
 103
 104         memory {
 105                 #address-cells = <1>;
 106                 #size-cells = <1>;
 107                 ranges = <0x00000000 0x80000000 0x40000000>;
 108                 device_type = "memory";
 109                 reg = <0x80000000 0x20000000>;  /* 512MiB */
 110         };
 111
 112         reserved-memory {
 113                 #address-cells = <1>;
 114                 #size-cells = <1>;
 115                 ranges;
 116                 /*
 117                  * Move frame buffer out of IOC aperture (0x8z-0xAz).
 118                  */
 119                 frame_buffer: frame_buffer@be000000 {
 120                         compatible = "shared-dma-pool";
 121                         reg = <0xbe000000 0x2000000>;
 122                         no-map;
 123                 };
 124         };
 125 };