2 # Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
4 # This program is free software; you can redistribute it and/or modify
5 # it under the terms of the GNU General Public License version 2 as
6 # published by the Free Software Foundation.
12 select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC
13 select BUILDTIME_EXTABLE_SORT
14 select CLONE_BACKWARDS
16 select GENERIC_ATOMIC64 if !ISA_ARCV2 || !(ARC_HAS_LL64 && ARC_HAS_LLSC)
17 select GENERIC_CLOCKEVENTS
18 select GENERIC_FIND_FIRST_BIT
19 # for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP
20 select GENERIC_IRQ_SHOW
21 select GENERIC_PCI_IOMAP
22 select GENERIC_PENDING_IRQ if SMP
23 select GENERIC_SMP_IDLE_THREAD
25 select HAVE_ARCH_TRACEHOOK
26 select HAVE_FUTEX_CMPXCHG
27 select HAVE_IOREMAP_PROT
29 select HAVE_KRETPROBES
31 select HAVE_MOD_ARCH_SPECIFIC if ARC_DW2_UNWIND
33 select HAVE_PERF_EVENTS
34 select HANDLE_DOMAIN_IRQ
36 select MODULES_USE_ELF_RELA
39 select OF_EARLY_FLATTREE
40 select OF_RESERVED_MEM
41 select PERF_USE_VMALLOC
42 select HAVE_DEBUG_STACKOVERFLOW
43 select HAVE_GENERIC_DMA_COHERENT
44 select HAVE_KERNEL_GZIP
45 select HAVE_KERNEL_LZMA
50 config TRACE_IRQFLAGS_SUPPORT
53 config LOCKDEP_SUPPORT
56 config SCHED_OMIT_FRAME_POINTER
62 config RWSEM_GENERIC_SPINLOCK
65 config ARCH_DISCONTIGMEM_ENABLE
68 config ARCH_FLATMEM_ENABLE
77 config GENERIC_CALIBRATE_DELAY
80 config GENERIC_HWEIGHT
83 config STACKTRACE_SUPPORT
87 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
92 source "kernel/Kconfig.freezer"
94 menu "ARC Architecture Configuration"
96 menu "ARC Platform/SoC/Board"
98 source "arch/arc/plat-sim/Kconfig"
99 source "arch/arc/plat-tb10x/Kconfig"
100 source "arch/arc/plat-axs10x/Kconfig"
101 #New platform adds here
102 source "arch/arc/plat-eznps/Kconfig"
107 prompt "ARC Instruction Set"
108 default ISA_ARCOMPACT
112 select CPU_NO_EFFICIENT_FFS
114 The original ARC ISA of ARC600/700 cores
118 select ARC_TIMERS_64BIT
120 ISA for the Next Generation ARC-HS cores
124 menu "ARC CPU Configuration"
128 default ARC_CPU_770 if ISA_ARCOMPACT
129 default ARC_CPU_HS if ISA_ARCV2
137 Support for ARC750 core
143 Support for ARC770 core introduced with Rel 4.10 (Summer 2011)
144 This core has a bunch of cool new features:
145 -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4)
146 Shared Address Spaces (for sharing TLB entires in MMU)
147 -Caches: New Prog Model, Region Flush
148 -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr
156 Support for ARC HS38x Cores based on ARCv2 ISA
157 The notable features are:
158 - SMP configurations of upto 4 core with coherency
159 - Optional L2 Cache and IO-Coherency
160 - Revised Interrupt Architecture (multiple priorites, reg banks,
161 auto stack switch, auto regfile save/restore)
162 - MMUv4 (PIPT dcache, Huge Pages)
164 * 64bit load/store: LDD, STD
165 * Hardware assisted divide/remainder: DIV, REM
166 * Function prologue/epilogue: ENTER_S, LEAVE_S
167 * IRQ enable/disable: CLRI, SETI
168 * pop count: FFS, FLS
169 * SETcc, BMSKN, XBFU...
173 config CPU_BIG_ENDIAN
174 bool "Enable Big Endian Mode"
177 Build kernel for Big Endian Mode of ARC CPU
180 bool "Symmetric Multi-Processing"
182 select ARC_HAS_COH_CACHES if ISA_ARCV2
183 select ARC_MCIP if ISA_ARCV2
185 This enables support for systems with more than one CPU.
189 config ARC_HAS_COH_CACHES
193 int "Maximum number of CPUs (2-4096)"
197 config ARC_SMP_HALT_ON_RESET
198 bool "Enable Halt-on-reset boot mode"
199 default y if ARC_UBOOT_SUPPORT
201 In SMP configuration cores can be configured as Halt-on-reset
202 or they could all start at same time. For Halt-on-reset, non
203 masters are parked until Master kicks them so they can start of
204 at designated entry point. For other case, all jump to common
205 entry point and spin wait for Master's signal.
210 bool "ARConnect Multicore IP (MCIP) Support "
214 This IP block enables SMP in ARC-HS38 cores.
215 It provides for cross-core interrupts, multi-core debug
216 hardware semaphores, shared memory,....
219 bool "Enable Cache Support"
221 # if SMP, cache enabled ONLY if ARC implementation has cache coherency
222 depends on !SMP || ARC_HAS_COH_CACHES
226 config ARC_CACHE_LINE_SHIFT
227 int "Cache Line Length (as power of 2)"
231 Starting with ARC700 4.9, Cache line length is configurable,
232 This option specifies "N", with Line-len = 2 power N
233 So line lengths of 32, 64, 128 are specified by 5,6,7, respectively
234 Linux only supports same line lengths for I and D caches.
236 config ARC_HAS_ICACHE
237 bool "Use Instruction Cache"
240 config ARC_HAS_DCACHE
241 bool "Use Data Cache"
244 config ARC_CACHE_PAGES
245 bool "Per Page Cache Control"
247 depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE
249 This can be used to over-ride the global I/D Cache Enable on a
250 per-page basis (but only for pages accessed via MMU such as
251 Kernel Virtual address or User Virtual Address)
252 TLB entries have a per-page Cache Enable Bit.
253 Note that Global I/D ENABLE + Per Page DISABLE works but corollary
254 Global DISABLE + Per Page ENABLE won't work
256 config ARC_CACHE_VIPT_ALIASING
257 bool "Support VIPT Aliasing D$"
258 depends on ARC_HAS_DCACHE && ISA_ARCOMPACT
266 Single Cycle RAMS to store Fast Path Code
270 int "ICCM Size in KB"
272 depends on ARC_HAS_ICCM
277 Single Cycle RAMS to store Fast Path Data
281 int "DCCM Size in KB"
283 depends on ARC_HAS_DCCM
286 hex "DCCM map address"
288 depends on ARC_HAS_DCCM
292 default ARC_MMU_V3 if ARC_CPU_770
293 default ARC_MMU_V2 if ARC_CPU_750D
294 default ARC_MMU_V4 if ARC_CPU_HS
306 Fixed the deficiency of v1 - possible thrashing in memcpy sceanrio
307 when 2 D-TLB and 1 I-TLB entries index into same 2way set.
311 depends on ARC_CPU_770
313 Introduced with ARC700 4.10: New Features
314 Variable Page size (1k-16k), var JTLB size 128 x (2 or 4)
315 Shared Address Spaces (SASID)
327 prompt "MMU Page Size"
328 default ARC_PAGE_SIZE_8K
330 config ARC_PAGE_SIZE_8K
333 Choose between 8k vs 16k
335 config ARC_PAGE_SIZE_16K
337 depends on ARC_MMU_V3 || ARC_MMU_V4
339 config ARC_PAGE_SIZE_4K
341 depends on ARC_MMU_V3 || ARC_MMU_V4
346 prompt "MMU Super Page Size"
347 depends on ISA_ARCV2 && TRANSPARENT_HUGEPAGE
348 default ARC_HUGEPAGE_2M
350 config ARC_HUGEPAGE_2M
353 config ARC_HUGEPAGE_16M
359 int "Maximum NUMA Nodes (as a power of 2)"
360 default "0" if !DISCONTIGMEM
361 default "1" if DISCONTIGMEM
362 depends on NEED_MULTIPLE_NODES
364 Accessing memory beyond 1GB (with or w/o PAE) requires 2 memory
369 config ARC_COMPACT_IRQ_LEVELS
370 bool "Setup Timer IRQ as high Priority"
372 # if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy
375 config ARC_FPU_SAVE_RESTORE
376 bool "Enable FPU state persistence across context switch"
379 Double Precision Floating Point unit had dedictaed regs which
380 need to be saved/restored across context-switch.
381 Note that ARC FPU is overly simplistic, unlike say x86, which has
382 hardware pieces to allow software to conditionally save/restore,
383 based on actual usage of FPU by a task. Thus our implemn does
384 this for all tasks in system.
392 bool "Insn: LLOCK/SCOND (efficient atomic ops)"
394 depends on !ARC_CANT_LLSC
397 bool "Insn: SWAPE (endian-swap)"
403 bool "Insn: 64bit LDD/STD"
405 Enable gcc to generate 64-bit load/store instructions
406 ISA mandates even/odd registers to allow encoding of two
407 dest operands with 2 possible source operands.
410 config ARC_HAS_DIV_REM
411 bool "Insn: div, divu, rem, remu"
414 config ARC_NUMBER_OF_INTERRUPTS
415 int "Number of interrupts"
419 This defines the number of interrupts on the ARCv2HS core.
420 It affects the size of vector table.
421 The initial 8 IRQs are fixed (Timer, ICI etc) and although configurable
422 in hardware, it keep things simple for Linux to assume they are always
427 endmenu # "ARC CPU Configuration"
429 config LINUX_LINK_BASE
430 hex "Linux Link Address"
433 ARC700 divides the 32 bit phy address space into two equal halves
434 -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU
435 -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel
436 Typically Linux kernel is linked at the start of untransalted addr,
437 hence the default value of 0x8zs.
438 However some customers have peripherals mapped at this addr, so
439 Linux needs to be scooted a bit.
440 If you don't know what the above means, leave this setting alone.
441 This needs to match memory start address specified in Device Tree
444 bool "High Memory Support"
445 select ARCH_DISCONTIGMEM_ENABLE
447 With ARC 2G:2G address split, only upper 2G is directly addressable by
448 kernel. Enable this to potentially allow access to rest of 2G and PAE
452 bool "Support for the 40-bit Physical Address Extension"
456 Enable access to physical memory beyond 4G, only supported on
457 ARC cores with 40 bit Physical Addressing support
459 config ARCH_PHYS_ADDR_T_64BIT
460 def_bool ARC_HAS_PAE40
462 config ARCH_DMA_ADDR_T_64BIT
465 config ARC_PLAT_NEEDS_PHYS_TO_DMA
468 config ARC_KVADDR_SIZE
469 int "Kernel Virtaul Address Space size (MB)"
473 The kernel address space is carved out of 256MB of translated address
474 space for catering to vmalloc, modules, pkmap, fixmap. This however may
475 not suffice vmalloc requirements of a 4K CPU EZChip system. So allow
476 this to be stretched to 512 MB (by extending into the reserved
479 config ARC_CURR_IN_REG
480 bool "Dedicate Register r25 for current_task pointer"
483 This reserved Register R25 to point to Current Task in
484 kernel mode. This saves memory access for each such access
487 config ARC_EMUL_UNALIGNED
488 bool "Emulate unaligned memory access (userspace only)"
490 select SYSCTL_ARCH_UNALIGN_NO_WARN
491 select SYSCTL_ARCH_UNALIGN_ALLOW
492 depends on ISA_ARCOMPACT
494 This enables misaligned 16 & 32 bit memory access from user space.
495 Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide
496 potential bugs in code
499 int "Timer Frequency"
502 config ARC_METAWARE_HLINK
503 bool "Support for Metaware debugger assisted Host access"
506 This options allows a Linux userland apps to directly access
507 host file system (open/creat/read/write etc) with help from
508 Metaware Debugger. This can come in handy for Linux-host communication
509 when there is no real usable peripheral such as EMAC.
517 config ARC_DW2_UNWIND
518 bool "Enable DWARF specific kernel stack unwind"
522 Compiles the kernel with DWARF unwind information and can be used
523 to get stack backtraces.
525 If you say Y here the resulting kernel image will be slightly larger
526 but not slower, and it will give very useful debugging information.
527 If you don't debug the kernel, you can say N, but we may not be able
528 to solve problems without frame unwind information
530 config ARC_DBG_TLB_PARANOIA
531 bool "Paranoia Checks in Low Level TLB Handlers"
536 config ARC_UBOOT_SUPPORT
537 bool "Support uboot arg Handling"
540 ARC Linux by default checks for uboot provided args as pointers to
541 external cmdline or DTB. This however breaks in absence of uboot,
542 when booting from Metaware debugger directly, as the registers are
543 not zeroed out on reset by mdb and/or ARCv2 based cores. The bogus
544 registers look like uboot args to kernel which then chokes.
545 So only enable the uboot arg checking/processing if users are sure
546 of uboot being in play.
548 config ARC_BUILTIN_DTB_NAME
549 string "Built in DTB"
551 Set the name of the DTB to embed in the vmlinux binary
552 Leaving it blank selects the minimal "skeleton" dtb
554 source "kernel/Kconfig.preempt"
556 menu "Executable file formats"
557 source "fs/Kconfig.binfmt"
560 endmenu # "ARC Architecture Configuration"
564 config FORCE_MAX_ZONEORDER
565 int "Maximum zone order"
566 default "12" if ARC_HUGEPAGE_16M
570 source "drivers/Kconfig"
575 bool "PCI support" if MIGHT_HAVE_PCI
577 PCI is the name of a bus system, i.e., the way the CPU talks to
578 the other stuff inside your box. Find out if your board/platform
581 Note: PCIe support for Synopsys Device will be available only
582 when HAPS DX is configured with PCIe RC bitmap. If you have PCI,
588 source "drivers/pci/Kconfig"
593 source "arch/arc/Kconfig.debug"
594 source "security/Kconfig"
595 source "crypto/Kconfig"
597 source "kernel/power/Kconfig"