1 #include <linux/module.h>
2 #include <linux/types.h>
3 #include <linux/kernel.h>
4 #include <linux/sched.h>
5 #include <asm/ptrace.h>
7 #include <linux/uaccess.h>
10 #include <math-emu/soft-fp.h>
11 #include <math-emu/single.h>
12 #include <math-emu/double.h>
30 #define FOP_FNC_ADDx 0
31 #define FOP_FNC_CVTQL 0
32 #define FOP_FNC_SUBx 1
33 #define FOP_FNC_MULx 2
34 #define FOP_FNC_DIVx 3
35 #define FOP_FNC_CMPxUN 4
36 #define FOP_FNC_CMPxEQ 5
37 #define FOP_FNC_CMPxLT 6
38 #define FOP_FNC_CMPxLE 7
39 #define FOP_FNC_SQRTx 11
40 #define FOP_FNC_CVTxS 12
41 #define FOP_FNC_CVTxT 14
42 #define FOP_FNC_CVTxQ 15
44 #define MISC_TRAPB 0x0000
45 #define MISC_EXCB 0x0400
47 extern unsigned long alpha_read_fp_reg (unsigned long reg);
48 extern void alpha_write_fp_reg (unsigned long reg, unsigned long val);
49 extern unsigned long alpha_read_fp_reg_s (unsigned long reg);
50 extern void alpha_write_fp_reg_s (unsigned long reg, unsigned long val);
55 MODULE_DESCRIPTION("FP Software completion module");
57 extern long (*alpha_fp_emul_imprecise)(struct pt_regs *, unsigned long);
58 extern long (*alpha_fp_emul) (unsigned long pc);
60 static long (*save_emul_imprecise)(struct pt_regs *, unsigned long);
61 static long (*save_emul) (unsigned long pc);
63 long do_alpha_fp_emul_imprecise(struct pt_regs *, unsigned long);
64 long do_alpha_fp_emul(unsigned long);
68 save_emul_imprecise = alpha_fp_emul_imprecise;
69 save_emul = alpha_fp_emul;
70 alpha_fp_emul_imprecise = do_alpha_fp_emul_imprecise;
71 alpha_fp_emul = do_alpha_fp_emul;
75 void cleanup_module(void)
77 alpha_fp_emul_imprecise = save_emul_imprecise;
78 alpha_fp_emul = save_emul;
81 #undef alpha_fp_emul_imprecise
82 #define alpha_fp_emul_imprecise do_alpha_fp_emul_imprecise
84 #define alpha_fp_emul do_alpha_fp_emul
90 * Emulate the floating point instruction at address PC. Returns -1 if the
91 * instruction to be emulated is illegal (such as with the opDEC trap), else
92 * the SI_CODE for a SIGFPE signal, else 0 if everything's ok.
94 * Notice that the kernel does not and cannot use FP regs. This is good
95 * because it means that instead of saving/restoring all fp regs, we simply
96 * stick the result of the operation into the appropriate register.
99 alpha_fp_emul (unsigned long pc)
102 FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SR);
103 FP_DECL_D(DA); FP_DECL_D(DB); FP_DECL_D(DR);
105 unsigned long fa, fb, fc, func, mode, src;
106 unsigned long res, va, vb, vc, swcr, fpcr;
110 get_user(insn, (__u32 __user *)pc);
111 fc = (insn >> 0) & 0x1f; /* destination register */
112 fb = (insn >> 16) & 0x1f;
113 fa = (insn >> 21) & 0x1f;
114 func = (insn >> 5) & 0xf;
115 src = (insn >> 9) & 0x3;
116 mode = (insn >> 11) & 0x3;
119 swcr = swcr_update_status(current_thread_info()->ieee_state, fpcr);
122 /* Dynamic -- get rounding mode from fpcr. */
123 mode = (fpcr >> FPCR_DYN_SHIFT) & 3;
128 va = alpha_read_fp_reg_s(fa);
129 vb = alpha_read_fp_reg_s(fb);
131 FP_UNPACK_SP(SA, &va);
132 FP_UNPACK_SP(SB, &vb);
136 FP_SUB_S(SR, SA, SB);
140 FP_ADD_S(SR, SA, SB);
144 FP_MUL_S(SR, SA, SB);
148 FP_DIV_S(SR, SA, SB);
158 va = alpha_read_fp_reg(fa);
159 vb = alpha_read_fp_reg(fb);
161 if ((func & ~3) == FOP_FNC_CMPxUN) {
162 FP_UNPACK_RAW_DP(DA, &va);
163 FP_UNPACK_RAW_DP(DB, &vb);
164 if (!DA_e && !_FP_FRAC_ZEROP_1(DA)) {
165 FP_SET_EXCEPTION(FP_EX_DENORM);
167 _FP_FRAC_SET_1(DA, _FP_ZEROFRAC_1);
169 if (!DB_e && !_FP_FRAC_ZEROP_1(DB)) {
170 FP_SET_EXCEPTION(FP_EX_DENORM);
172 _FP_FRAC_SET_1(DB, _FP_ZEROFRAC_1);
174 FP_CMP_D(res, DA, DB, 3);
175 vc = 0x4000000000000000UL;
176 /* CMPTEQ, CMPTUN don't trap on QNaN,
177 while CMPTLT and CMPTLE do */
181 || FP_ISSIGNAN_D(DB))) {
182 FP_SET_EXCEPTION(FP_EX_INVALID);
185 case FOP_FNC_CMPxUN: if (res != 3) vc = 0; break;
186 case FOP_FNC_CMPxEQ: if (res) vc = 0; break;
187 case FOP_FNC_CMPxLT: if (res != -1) vc = 0; break;
188 case FOP_FNC_CMPxLE: if ((long)res > 0) vc = 0; break;
193 FP_UNPACK_DP(DA, &va);
194 FP_UNPACK_DP(DB, &vb);
198 FP_SUB_D(DR, DA, DB);
202 FP_ADD_D(DR, DA, DB);
206 FP_MUL_D(DR, DA, DB);
210 FP_DIV_D(DR, DA, DB);
218 /* It is irritating that DEC encoded CVTST with
219 SRC == T_floating. It is also interesting that
220 the bit used to tell the two apart is /U... */
222 FP_CONV(S,D,1,1,SR,DB);
225 vb = alpha_read_fp_reg_s(fb);
226 FP_UNPACK_SP(SB, &vb);
229 DR_e = DB_e + (1024 - 128);
230 DR_f = SB_f << (52 - 23);
235 if (DB_c == FP_CLS_NAN
236 && (_FP_FRAC_HIGH_RAW_D(DB) & _FP_QNANBIT_D)) {
237 /* AAHB Table B-2 says QNaN should not trigger INV */
240 FP_TO_INT_ROUND_D(vc, DB, 64, 2);
246 vb = alpha_read_fp_reg(fb);
250 /* Notice: We can get here only due to an integer
251 overflow. Such overflows are reported as invalid
252 ops. We return the result the hw would have
254 vc = ((vb & 0xc0000000) << 32 | /* sign and msb */
255 (vb & 0x3fffffff) << 29); /* rest of the int */
256 FP_SET_EXCEPTION (FP_EX_INVALID);
260 FP_FROM_INT_S(SR, ((long)vb), 64, long);
264 FP_FROM_INT_D(DR, ((long)vb), 64, long);
273 if ((_fex & FP_EX_UNDERFLOW) && (swcr & IEEE_MAP_UMZ))
275 alpha_write_fp_reg_s(fc, vc);
280 if ((_fex & FP_EX_UNDERFLOW) && (swcr & IEEE_MAP_UMZ))
283 alpha_write_fp_reg(fc, vc);
287 * Take the appropriate action for each possible
288 * floating-point result:
290 * - Set the appropriate bits in the FPCR
291 * - If the specified exception is enabled in the FPCR,
292 * return. The caller (entArith) will dispatch
293 * the appropriate signal to the translated program.
295 * In addition, properly track the exception state in software
296 * as described in the Alpha Architecture Handbook section 4.7.7.3.
300 /* Record exceptions in software control word. */
301 swcr |= (_fex << IEEE_STATUS_TO_EXCSUM_SHIFT);
302 current_thread_info()->ieee_state
303 |= (_fex << IEEE_STATUS_TO_EXCSUM_SHIFT);
305 /* Update hardware control register. */
306 fpcr &= (~FPCR_MASK | FPCR_DYN_MASK);
307 fpcr |= ieee_swcr_to_fpcr(swcr);
310 /* Do we generate a signal? */
311 _fex = _fex & swcr & IEEE_TRAP_ENABLE_MASK;
314 if (_fex & IEEE_TRAP_ENABLE_DNO) si_code = FPE_FLTUND;
315 if (_fex & IEEE_TRAP_ENABLE_INE) si_code = FPE_FLTRES;
316 if (_fex & IEEE_TRAP_ENABLE_UNF) si_code = FPE_FLTUND;
317 if (_fex & IEEE_TRAP_ENABLE_OVF) si_code = FPE_FLTOVF;
318 if (_fex & IEEE_TRAP_ENABLE_DZE) si_code = FPE_FLTDIV;
319 if (_fex & IEEE_TRAP_ENABLE_INV) si_code = FPE_FLTINV;
325 /* We used to write the destination register here, but DEC FORTRAN
326 requires that the result *always* be written... so we do the write
327 immediately after the operations above. */
332 printk(KERN_ERR "alpha_fp_emul: Invalid FP insn %#x at %#lx\n",
338 alpha_fp_emul_imprecise (struct pt_regs *regs, unsigned long write_mask)
340 unsigned long trigger_pc = regs->pc - 4;
341 unsigned long insn, opcode, rc, si_code = 0;
344 * Turn off the bits corresponding to registers that are the
345 * target of instructions that set bits in the exception
346 * summary register. We have some slack doing this because a
347 * register that is the target of a trapping instruction can
348 * be written at most once in the trap shadow.
350 * Branches, jumps, TRAPBs, EXCBs and calls to PALcode all
351 * bound the trap shadow, so we need not look any further than
352 * up to the first occurrence of such an instruction.
355 get_user(insn, (__u32 __user *)(trigger_pc));
362 case 0x30 ... 0x3f: /* branches */
366 switch (insn & 0xffff) {
380 write_mask &= ~(1UL << rc);
387 write_mask &= ~(1UL << (rc + 32));
391 /* Re-execute insns in the trap-shadow. */
392 regs->pc = trigger_pc + 4;
393 si_code = alpha_fp_emul(trigger_pc);