2 * arch/alpha/kernel/traps.c
4 * (C) Copyright 1994 Linus Torvalds
8 * This file initializes the trap entry points
11 #include <linux/jiffies.h>
13 #include <linux/sched/signal.h>
14 #include <linux/sched/debug.h>
15 #include <linux/tty.h>
16 #include <linux/delay.h>
17 #include <linux/extable.h>
18 #include <linux/kallsyms.h>
19 #include <linux/ratelimit.h>
21 #include <asm/gentrap.h>
22 #include <linux/uaccess.h>
23 #include <asm/unaligned.h>
24 #include <asm/sysinfo.h>
25 #include <asm/hwrpb.h>
26 #include <asm/mmu_context.h>
27 #include <asm/special_insns.h>
31 /* Work-around for some SRMs which mishandle opDEC faults. */
38 __asm__ __volatile__ (
39 /* Load the address of... */
41 /* A stub instruction fault handler. Just add 4 to the
47 /* Install the instruction fault handler. */
49 " call_pal %[wrent]\n"
50 /* With that in place, the fault from the round-to-minf fp
51 insn will arrive either at the "lda 4" insn (bad) or one
52 past that (good). This places the correct fixup in %0. */
54 " cvttq/svm $f31,$f31\n"
56 : [fix] "=r" (opDEC_fix)
57 : [rti] "n" (PAL_rti), [wrent] "n" (PAL_wrent)
58 : "$0", "$1", "$16", "$17", "$22", "$23", "$24", "$25");
61 printk("opDEC fixup enabled.\n");
65 dik_show_regs(struct pt_regs *regs, unsigned long *r9_15)
67 printk("pc = [<%016lx>] ra = [<%016lx>] ps = %04lx %s\n",
68 regs->pc, regs->r26, regs->ps, print_tainted());
69 printk("pc is at %pSR\n", (void *)regs->pc);
70 printk("ra is at %pSR\n", (void *)regs->r26);
71 printk("v0 = %016lx t0 = %016lx t1 = %016lx\n",
72 regs->r0, regs->r1, regs->r2);
73 printk("t2 = %016lx t3 = %016lx t4 = %016lx\n",
74 regs->r3, regs->r4, regs->r5);
75 printk("t5 = %016lx t6 = %016lx t7 = %016lx\n",
76 regs->r6, regs->r7, regs->r8);
79 printk("s0 = %016lx s1 = %016lx s2 = %016lx\n",
80 r9_15[9], r9_15[10], r9_15[11]);
81 printk("s3 = %016lx s4 = %016lx s5 = %016lx\n",
82 r9_15[12], r9_15[13], r9_15[14]);
83 printk("s6 = %016lx\n", r9_15[15]);
86 printk("a0 = %016lx a1 = %016lx a2 = %016lx\n",
87 regs->r16, regs->r17, regs->r18);
88 printk("a3 = %016lx a4 = %016lx a5 = %016lx\n",
89 regs->r19, regs->r20, regs->r21);
90 printk("t8 = %016lx t9 = %016lx t10= %016lx\n",
91 regs->r22, regs->r23, regs->r24);
92 printk("t11= %016lx pv = %016lx at = %016lx\n",
93 regs->r25, regs->r27, regs->r28);
94 printk("gp = %016lx sp = %p\n", regs->gp, regs+1);
101 static char * ireg_name[] = {"v0", "t0", "t1", "t2", "t3", "t4", "t5", "t6",
102 "t7", "s0", "s1", "s2", "s3", "s4", "s5", "s6",
103 "a0", "a1", "a2", "a3", "a4", "a5", "t8", "t9",
104 "t10", "t11", "ra", "pv", "at", "gp", "sp", "zero"};
108 dik_show_code(unsigned int *pc)
113 for (i = -6; i < 2; i++) {
115 if (__get_user(insn, (unsigned int __user *)pc + i))
117 printk("%c%08x%c", i ? ' ' : '<', insn, i ? ' ' : '>');
123 dik_show_trace(unsigned long *sp)
127 while (0x1ff8 & (unsigned long) sp) {
128 extern char _stext[], _etext[];
129 unsigned long tmp = *sp;
131 if (tmp < (unsigned long) &_stext)
133 if (tmp >= (unsigned long) &_etext)
135 printk("[<%lx>] %pSR\n", tmp, (void *)tmp);
144 static int kstack_depth_to_print = 24;
146 void show_stack(struct task_struct *task, unsigned long *sp)
148 unsigned long *stack;
152 * debugging aid: "show_stack(NULL);" prints the
153 * back trace for this cpu.
156 sp=(unsigned long*)&sp;
159 for(i=0; i < kstack_depth_to_print; i++) {
160 if (((long) stack & (THREAD_SIZE-1)) == 0)
162 if (i && ((i % 4) == 0))
164 printk("%016lx ", *stack++);
171 die_if_kernel(char * str, struct pt_regs *regs, long err, unsigned long *r9_15)
176 printk("CPU %d ", hard_smp_processor_id());
178 printk("%s(%d): %s %ld\n", current->comm, task_pid_nr(current), str, err);
179 dik_show_regs(regs, r9_15);
180 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
181 dik_show_trace((unsigned long *)(regs+1));
182 dik_show_code((unsigned int *)regs->pc);
184 if (test_and_set_thread_flag (TIF_DIE_IF_KERNEL)) {
185 printk("die_if_kernel recursion detected.\n");
192 #ifndef CONFIG_MATHEMU
193 static long dummy_emul(void) { return 0; }
194 long (*alpha_fp_emul_imprecise)(struct pt_regs *regs, unsigned long writemask)
195 = (void *)dummy_emul;
196 long (*alpha_fp_emul) (unsigned long pc)
197 = (void *)dummy_emul;
199 long alpha_fp_emul_imprecise(struct pt_regs *regs, unsigned long writemask);
200 long alpha_fp_emul (unsigned long pc);
204 do_entArith(unsigned long summary, unsigned long write_mask,
205 struct pt_regs *regs)
207 long si_code = FPE_FLTINV;
211 /* Software-completion summary bit is set, so try to
212 emulate the instruction. If the processor supports
213 precise exceptions, we don't have to search. */
214 if (!amask(AMASK_PRECISE_TRAP))
215 si_code = alpha_fp_emul(regs->pc - 4);
217 si_code = alpha_fp_emul_imprecise(regs, write_mask);
221 die_if_kernel("Arithmetic fault", regs, 0, NULL);
223 info.si_signo = SIGFPE;
225 info.si_code = si_code;
226 info.si_addr = (void __user *) regs->pc;
227 send_sig_info(SIGFPE, &info, current);
231 do_entIF(unsigned long type, struct pt_regs *regs)
236 if ((regs->ps & ~IPL_MAX) == 0) {
238 const unsigned int *data
239 = (const unsigned int *) regs->pc;
240 printk("Kernel bug at %s:%d\n",
241 (const char *)(data[1] | (long)data[2] << 32),
244 #ifdef CONFIG_ALPHA_WTINT
246 /* If CALL_PAL WTINT is totally unsupported by the
247 PALcode, e.g. MILO, "emulate" it by overwriting
250 = (unsigned int *) regs->pc - 1;
251 if (*pinsn == PAL_wtint) {
252 *pinsn = 0x47e01400; /* mov 0,$0 */
258 #endif /* ALPHA_WTINT */
259 die_if_kernel((type == 1 ? "Kernel Bug" : "Instruction fault"),
264 case 0: /* breakpoint */
265 info.si_signo = SIGTRAP;
267 info.si_code = TRAP_BRKPT;
269 info.si_addr = (void __user *) regs->pc;
271 if (ptrace_cancel_bpt(current)) {
272 regs->pc -= 4; /* make pc point to former bpt */
275 send_sig_info(SIGTRAP, &info, current);
278 case 1: /* bugcheck */
279 info.si_signo = SIGTRAP;
281 info.si_code = __SI_FAULT;
282 info.si_addr = (void __user *) regs->pc;
284 send_sig_info(SIGTRAP, &info, current);
287 case 2: /* gentrap */
288 info.si_addr = (void __user *) regs->pc;
289 info.si_trapno = regs->r16;
290 switch ((long) regs->r16) {
347 info.si_signo = signo;
350 info.si_addr = (void __user *) regs->pc;
351 send_sig_info(signo, &info, current);
355 if (implver() == IMPLVER_EV4) {
358 /* The some versions of SRM do not handle
359 the opDEC properly - they return the PC of the
360 opDEC fault, not the instruction after as the
361 Alpha architecture requires. Here we fix it up.
362 We do this by intentionally causing an opDEC
363 fault during the boot sequence and testing if
364 we get the correct PC. If not, we set a flag
365 to correct it every time through. */
366 regs->pc += opDEC_fix;
368 /* EV4 does not implement anything except normal
369 rounding. Everything else will come here as
370 an illegal instruction. Emulate them. */
371 si_code = alpha_fp_emul(regs->pc - 4);
375 info.si_signo = SIGFPE;
377 info.si_code = si_code;
378 info.si_addr = (void __user *) regs->pc;
379 send_sig_info(SIGFPE, &info, current);
385 case 3: /* FEN fault */
386 /* Irritating users can call PAL_clrfen to disable the
387 FPU for the process. The kernel will then trap in
388 do_switch_stack and undo_switch_stack when we try
389 to save and restore the FP registers.
391 Given that GCC by default generates code that uses the
392 FP registers, PAL_clrfen is not useful except for DoS
393 attacks. So turn the bleeding FPU back on and be done
395 current_thread_info()->pcb.flags |= 1;
396 __reload_thread(¤t_thread_info()->pcb);
400 default: /* unexpected instruction-fault type */
404 info.si_signo = SIGILL;
406 info.si_code = ILL_ILLOPC;
407 info.si_addr = (void __user *) regs->pc;
408 send_sig_info(SIGILL, &info, current);
411 /* There is an ifdef in the PALcode in MILO that enables a
412 "kernel debugging entry point" as an unprivileged call_pal.
414 We don't want to have anything to do with it, but unfortunately
415 several versions of MILO included in distributions have it enabled,
416 and if we don't put something on the entry point we'll oops. */
419 do_entDbg(struct pt_regs *regs)
423 die_if_kernel("Instruction fault", regs, 0, NULL);
425 info.si_signo = SIGILL;
427 info.si_code = ILL_ILLOPC;
428 info.si_addr = (void __user *) regs->pc;
429 force_sig_info(SIGILL, &info, current);
434 * entUna has a different register layout to be reasonably simple. It
435 * needs access to all the integer registers (the kernel doesn't use
436 * fp-regs), and it needs to have them in order for simpler access.
438 * Due to the non-standard register layout (and because we don't want
439 * to handle floating-point regs), user-mode unaligned accesses are
440 * handled separately by do_entUnaUser below.
442 * Oh, btw, we don't handle the "gp" register correctly, but if we fault
443 * on a gp-register unaligned load/store, something is _very_ wrong
444 * in the kernel anyway..
447 unsigned long regs[32];
448 unsigned long ps, pc, gp, a0, a1, a2;
451 struct unaligned_stat {
452 unsigned long count, va, pc;
456 /* Macro for exception fixup code to access integer registers. */
457 #define una_reg(r) (_regs[(r) >= 16 && (r) <= 18 ? (r)+19 : (r)])
461 do_entUna(void * va, unsigned long opcode, unsigned long reg,
462 struct allregs *regs)
464 long error, tmp1, tmp2, tmp3, tmp4;
465 unsigned long pc = regs->pc - 4;
466 unsigned long *_regs = regs->regs;
467 const struct exception_table_entry *fixup;
469 unaligned[0].count++;
470 unaligned[0].va = (unsigned long) va;
471 unaligned[0].pc = pc;
473 /* We don't want to use the generic get/put unaligned macros as
474 we want to trap exceptions. Only if we actually get an
475 exception will we decide whether we should have caught it. */
478 case 0x0c: /* ldwu */
479 __asm__ __volatile__(
480 "1: ldq_u %1,0(%3)\n"
481 "2: ldq_u %2,1(%3)\n"
487 : "=r"(error), "=&r"(tmp1), "=&r"(tmp2)
491 una_reg(reg) = tmp1|tmp2;
495 __asm__ __volatile__(
496 "1: ldq_u %1,0(%3)\n"
497 "2: ldq_u %2,3(%3)\n"
503 : "=r"(error), "=&r"(tmp1), "=&r"(tmp2)
507 una_reg(reg) = (int)(tmp1|tmp2);
511 __asm__ __volatile__(
512 "1: ldq_u %1,0(%3)\n"
513 "2: ldq_u %2,7(%3)\n"
519 : "=r"(error), "=&r"(tmp1), "=&r"(tmp2)
523 una_reg(reg) = tmp1|tmp2;
526 /* Note that the store sequences do not indicate that they change
527 memory because it _should_ be affecting nothing in this context.
528 (Otherwise we have other, much larger, problems.) */
530 __asm__ __volatile__(
531 "1: ldq_u %2,1(%5)\n"
532 "2: ldq_u %1,0(%5)\n"
539 "3: stq_u %2,1(%5)\n"
540 "4: stq_u %1,0(%5)\n"
546 : "=r"(error), "=&r"(tmp1), "=&r"(tmp2),
547 "=&r"(tmp3), "=&r"(tmp4)
548 : "r"(va), "r"(una_reg(reg)), "0"(0));
554 __asm__ __volatile__(
555 "1: ldq_u %2,3(%5)\n"
556 "2: ldq_u %1,0(%5)\n"
563 "3: stq_u %2,3(%5)\n"
564 "4: stq_u %1,0(%5)\n"
570 : "=r"(error), "=&r"(tmp1), "=&r"(tmp2),
571 "=&r"(tmp3), "=&r"(tmp4)
572 : "r"(va), "r"(una_reg(reg)), "0"(0));
578 __asm__ __volatile__(
579 "1: ldq_u %2,7(%5)\n"
580 "2: ldq_u %1,0(%5)\n"
587 "3: stq_u %2,7(%5)\n"
588 "4: stq_u %1,0(%5)\n"
594 : "=r"(error), "=&r"(tmp1), "=&r"(tmp2),
595 "=&r"(tmp3), "=&r"(tmp4)
596 : "r"(va), "r"(una_reg(reg)), "0"(0));
602 printk("Bad unaligned kernel access at %016lx: %p %lx %lu\n",
603 pc, va, opcode, reg);
607 /* Ok, we caught the exception, but we don't want it. Is there
608 someone to pass it along to? */
609 if ((fixup = search_exception_tables(pc)) != 0) {
611 newpc = fixup_exception(una_reg, fixup, pc);
613 printk("Forwarding unaligned exception at %lx (%lx)\n",
621 * Yikes! No one to forward the exception to.
622 * Since the registers are in a weird format, dump them ourselves.
625 printk("%s(%d): unhandled unaligned exception\n",
626 current->comm, task_pid_nr(current));
628 printk("pc = [<%016lx>] ra = [<%016lx>] ps = %04lx\n",
629 pc, una_reg(26), regs->ps);
630 printk("r0 = %016lx r1 = %016lx r2 = %016lx\n",
631 una_reg(0), una_reg(1), una_reg(2));
632 printk("r3 = %016lx r4 = %016lx r5 = %016lx\n",
633 una_reg(3), una_reg(4), una_reg(5));
634 printk("r6 = %016lx r7 = %016lx r8 = %016lx\n",
635 una_reg(6), una_reg(7), una_reg(8));
636 printk("r9 = %016lx r10= %016lx r11= %016lx\n",
637 una_reg(9), una_reg(10), una_reg(11));
638 printk("r12= %016lx r13= %016lx r14= %016lx\n",
639 una_reg(12), una_reg(13), una_reg(14));
640 printk("r15= %016lx\n", una_reg(15));
641 printk("r16= %016lx r17= %016lx r18= %016lx\n",
642 una_reg(16), una_reg(17), una_reg(18));
643 printk("r19= %016lx r20= %016lx r21= %016lx\n",
644 una_reg(19), una_reg(20), una_reg(21));
645 printk("r22= %016lx r23= %016lx r24= %016lx\n",
646 una_reg(22), una_reg(23), una_reg(24));
647 printk("r25= %016lx r27= %016lx r28= %016lx\n",
648 una_reg(25), una_reg(27), una_reg(28));
649 printk("gp = %016lx sp = %p\n", regs->gp, regs+1);
651 dik_show_code((unsigned int *)pc);
652 dik_show_trace((unsigned long *)(regs+1));
654 if (test_and_set_thread_flag (TIF_DIE_IF_KERNEL)) {
655 printk("die_if_kernel recursion detected.\n");
663 * Convert an s-floating point value in memory format to the
664 * corresponding value in register format. The exponent
665 * needs to be remapped to preserve non-finite values
666 * (infinities, not-a-numbers, denormals).
668 static inline unsigned long
669 s_mem_to_reg (unsigned long s_mem)
671 unsigned long frac = (s_mem >> 0) & 0x7fffff;
672 unsigned long sign = (s_mem >> 31) & 0x1;
673 unsigned long exp_msb = (s_mem >> 30) & 0x1;
674 unsigned long exp_low = (s_mem >> 23) & 0x7f;
677 exp = (exp_msb << 10) | exp_low; /* common case */
679 if (exp_low == 0x7f) {
683 if (exp_low == 0x00) {
689 return (sign << 63) | (exp << 52) | (frac << 29);
693 * Convert an s-floating point value in register format to the
694 * corresponding value in memory format.
696 static inline unsigned long
697 s_reg_to_mem (unsigned long s_reg)
699 return ((s_reg >> 62) << 30) | ((s_reg << 5) >> 34);
703 * Handle user-level unaligned fault. Handling user-level unaligned
704 * faults is *extremely* slow and produces nasty messages. A user
705 * program *should* fix unaligned faults ASAP.
707 * Notice that we have (almost) the regular kernel stack layout here,
708 * so finding the appropriate registers is a little more difficult
709 * than in the kernel case.
711 * Finally, we handle regular integer load/stores only. In
712 * particular, load-linked/store-conditionally and floating point
713 * load/stores are not supported. The former make no sense with
714 * unaligned faults (they are guaranteed to fail) and I don't think
715 * the latter will occur in any decent program.
717 * Sigh. We *do* have to handle some FP operations, because GCC will
718 * uses them as temporary storage for integer memory to memory copies.
719 * However, we need to deal with stt/ldt and sts/lds only.
722 #define OP_INT_MASK ( 1L << 0x28 | 1L << 0x2c /* ldl stl */ \
723 | 1L << 0x29 | 1L << 0x2d /* ldq stq */ \
724 | 1L << 0x0c | 1L << 0x0d /* ldwu stw */ \
725 | 1L << 0x0a | 1L << 0x0e ) /* ldbu stb */
727 #define OP_WRITE_MASK ( 1L << 0x26 | 1L << 0x27 /* sts stt */ \
728 | 1L << 0x2c | 1L << 0x2d /* stl stq */ \
729 | 1L << 0x0d | 1L << 0x0e ) /* stw stb */
731 #define R(x) ((size_t) &((struct pt_regs *)0)->x)
733 static int unauser_reg_offsets[32] = {
734 R(r0), R(r1), R(r2), R(r3), R(r4), R(r5), R(r6), R(r7), R(r8),
735 /* r9 ... r15 are stored in front of regs. */
736 -56, -48, -40, -32, -24, -16, -8,
737 R(r16), R(r17), R(r18),
738 R(r19), R(r20), R(r21), R(r22), R(r23), R(r24), R(r25), R(r26),
739 R(r27), R(r28), R(gp),
746 do_entUnaUser(void __user * va, unsigned long opcode,
747 unsigned long reg, struct pt_regs *regs)
749 static DEFINE_RATELIMIT_STATE(ratelimit, 5 * HZ, 5);
751 unsigned long tmp1, tmp2, tmp3, tmp4;
752 unsigned long fake_reg, *reg_addr = &fake_reg;
756 /* Check the UAC bits to decide what the user wants us to do
757 with the unaliged access. */
759 if (!(current_thread_info()->status & TS_UAC_NOPRINT)) {
760 if (__ratelimit(&ratelimit)) {
761 printk("%s(%d): unaligned trap at %016lx: %p %lx %ld\n",
762 current->comm, task_pid_nr(current),
763 regs->pc - 4, va, opcode, reg);
766 if ((current_thread_info()->status & TS_UAC_SIGBUS))
768 /* Not sure why you'd want to use this, but... */
769 if ((current_thread_info()->status & TS_UAC_NOFIX))
772 /* Don't bother reading ds in the access check since we already
773 know that this came from the user. Also rely on the fact that
774 the page at TASK_SIZE is unmapped and so can't be touched anyway. */
775 if ((unsigned long)va >= TASK_SIZE)
778 ++unaligned[1].count;
779 unaligned[1].va = (unsigned long)va;
780 unaligned[1].pc = regs->pc - 4;
782 if ((1L << opcode) & OP_INT_MASK) {
783 /* it's an integer load/store */
785 reg_addr = (unsigned long *)
786 ((char *)regs + unauser_reg_offsets[reg]);
787 } else if (reg == 30) {
788 /* usp in PAL regs */
791 /* zero "register" */
796 /* We don't want to use the generic get/put unaligned macros as
797 we want to trap exceptions. Only if we actually get an
798 exception will we decide whether we should have caught it. */
801 case 0x0c: /* ldwu */
802 __asm__ __volatile__(
803 "1: ldq_u %1,0(%3)\n"
804 "2: ldq_u %2,1(%3)\n"
810 : "=r"(error), "=&r"(tmp1), "=&r"(tmp2)
814 *reg_addr = tmp1|tmp2;
818 __asm__ __volatile__(
819 "1: ldq_u %1,0(%3)\n"
820 "2: ldq_u %2,3(%3)\n"
826 : "=r"(error), "=&r"(tmp1), "=&r"(tmp2)
830 alpha_write_fp_reg(reg, s_mem_to_reg((int)(tmp1|tmp2)));
834 __asm__ __volatile__(
835 "1: ldq_u %1,0(%3)\n"
836 "2: ldq_u %2,7(%3)\n"
842 : "=r"(error), "=&r"(tmp1), "=&r"(tmp2)
846 alpha_write_fp_reg(reg, tmp1|tmp2);
850 __asm__ __volatile__(
851 "1: ldq_u %1,0(%3)\n"
852 "2: ldq_u %2,3(%3)\n"
858 : "=r"(error), "=&r"(tmp1), "=&r"(tmp2)
862 *reg_addr = (int)(tmp1|tmp2);
866 __asm__ __volatile__(
867 "1: ldq_u %1,0(%3)\n"
868 "2: ldq_u %2,7(%3)\n"
874 : "=r"(error), "=&r"(tmp1), "=&r"(tmp2)
878 *reg_addr = tmp1|tmp2;
881 /* Note that the store sequences do not indicate that they change
882 memory because it _should_ be affecting nothing in this context.
883 (Otherwise we have other, much larger, problems.) */
885 __asm__ __volatile__(
886 "1: ldq_u %2,1(%5)\n"
887 "2: ldq_u %1,0(%5)\n"
894 "3: stq_u %2,1(%5)\n"
895 "4: stq_u %1,0(%5)\n"
901 : "=r"(error), "=&r"(tmp1), "=&r"(tmp2),
902 "=&r"(tmp3), "=&r"(tmp4)
903 : "r"(va), "r"(*reg_addr), "0"(0));
909 fake_reg = s_reg_to_mem(alpha_read_fp_reg(reg));
913 __asm__ __volatile__(
914 "1: ldq_u %2,3(%5)\n"
915 "2: ldq_u %1,0(%5)\n"
922 "3: stq_u %2,3(%5)\n"
923 "4: stq_u %1,0(%5)\n"
929 : "=r"(error), "=&r"(tmp1), "=&r"(tmp2),
930 "=&r"(tmp3), "=&r"(tmp4)
931 : "r"(va), "r"(*reg_addr), "0"(0));
937 fake_reg = alpha_read_fp_reg(reg);
941 __asm__ __volatile__(
942 "1: ldq_u %2,7(%5)\n"
943 "2: ldq_u %1,0(%5)\n"
950 "3: stq_u %2,7(%5)\n"
951 "4: stq_u %1,0(%5)\n"
957 : "=r"(error), "=&r"(tmp1), "=&r"(tmp2),
958 "=&r"(tmp3), "=&r"(tmp4)
959 : "r"(va), "r"(*reg_addr), "0"(0));
965 /* What instruction were you trying to use, exactly? */
969 /* Only integer loads should get here; everyone else returns early. */
975 regs->pc -= 4; /* make pc point to faulting insn */
976 info.si_signo = SIGSEGV;
979 /* We need to replicate some of the logic in mm/fault.c,
980 since we don't have access to the fault code in the
981 exception handling return path. */
982 if ((unsigned long)va >= TASK_SIZE)
983 info.si_code = SEGV_ACCERR;
985 struct mm_struct *mm = current->mm;
986 down_read(&mm->mmap_sem);
987 if (find_vma(mm, (unsigned long)va))
988 info.si_code = SEGV_ACCERR;
990 info.si_code = SEGV_MAPERR;
991 up_read(&mm->mmap_sem);
994 send_sig_info(SIGSEGV, &info, current);
999 info.si_signo = SIGBUS;
1001 info.si_code = BUS_ADRALN;
1003 send_sig_info(SIGBUS, &info, current);
1010 /* Tell PAL-code what global pointer we want in the kernel. */
1011 register unsigned long gptr __asm__("$29");
1014 /* Hack for Multia (UDB) and JENSEN: some of their SRMs have
1015 a bug in the handling of the opDEC fault. Fix it up if so. */
1016 if (implver() == IMPLVER_EV4)