1 .. SPDX-License-Identifier: GPL-2.0
6 Memory at cx2341x chips
7 -----------------------
9 This section describes the cx2341x memory map and documents some of the
12 .. note:: the memory long words are little-endian ('intel format').
16 This information was figured out from searching through the memory
17 and registers, this information may not be correct and is certainly
18 not complete, and was not derived from anything more than searching
19 through the memory space with commands like:
23 ivtvctl -O min=0x02000000,max=0x020000ff
25 So take this as is, I'm always searching for more stuff, it's a large
31 The cx2341x exposes its entire 64M memory space to the PCI host via the PCI BAR0
32 (Base Address Register 0). The addresses here are offsets relative to the
37 0x00000000-0x00ffffff Encoder memory space
38 0x00000000-0x0003ffff Encode.rom
39 ???-??? MPEG buffer(s)
40 ???-??? Raw video capture buffer(s)
41 ???-??? Raw audio capture buffer(s)
42 ???-??? Display buffers (6 or 9)
44 0x01000000-0x01ffffff Decoder memory space
45 0x01000000-0x0103ffff Decode.rom
46 ???-??? MPEG buffers(s)
47 0x0114b000-0x0115afff Audio.rom (deprecated?)
49 0x02000000-0x0200ffff Register Space
54 The registers occupy the 64k space starting at the 0x02000000 offset from BAR0.
55 All of these registers are 32 bits wide.
59 DMA Registers 0x000-0xff:
62 0=reset/cancel, 1=read, 2=write, 4=stop
64 1=read busy, 2=write busy, 4=read error, 8=write error, 16=link list error
65 0x08 - pci DMA pointer for read link list
66 0x0c - pci DMA pointer for write link list
67 0x10 - read/write DMA enable:
68 1=read enable, 2=write enable
69 0x14 - always 0xffffffff, if set any lower instability occurs, 0x00 crashes
71 0x1c - always 0x20 or 32, smaller values slow down DMA transactions
72 0x20 - always value of 0x780a010a
73 0x24-0x3c - usually just random values???
74 0x40 - Interrupt status
75 0x44 - Write a bit here and shows up in Interrupt status 0x40
77 0x4C - always value of 0xfffdffff,
78 if changed to 0xffffffff DMA write interrupts break.
79 0x50 - always 0xffffffff
80 0x54 - always 0xffffffff (0x4c, 0x50, 0x54 seem like interrupt masks, are
81 3 processors on chip, Java ones, VPU, SPU, APU, maybe these are the
83 0x60-0x7C - random values
84 0x80 - first write linked list reg, for Encoder Memory addr
85 0x84 - first write linked list reg, for pci memory addr
86 0x88 - first write linked list reg, for length of buffer in memory addr
87 (|0x80000000 or this for last link)
88 0x8c-0xdc - rest of write linked list reg, 8 sets of 3 total, DMA goes here
89 from linked list addr in reg 0x0c, firmware must push through or
91 0xe0 - first (and only) read linked list reg, for pci memory addr
92 0xe4 - first (and only) read linked list reg, for Decoder memory addr
93 0xe8 - first (and only) read linked list reg, for length of buffer
94 0xec-0xff - Nothing seems to be in these registers, 0xec-f4 are 0x00000000.
96 Memory locations for Encoder Buffers 0x700-0x7ff:
98 These registers show offsets of memory locations pertaining to each
99 buffer area used for encoding, have to shift them by <<1 first.
101 - 0x07F8: Encoder SDRAM refresh
102 - 0x07FC: Encoder SDRAM pre-charge
104 Memory locations for Decoder Buffers 0x800-0x8ff:
106 These registers show offsets of memory locations pertaining to each
107 buffer area used for decoding, have to shift them by <<1 first.
109 - 0x08F8: Decoder SDRAM refresh
110 - 0x08FC: Decoder SDRAM pre-charge
112 Other memory locations:
114 - 0x2800: Video Display Module control
115 - 0x2D00: AO (audio output?) control
116 - 0x2D24: Bytes Flushed
117 - 0x7000: LSB I2C write clock bit (inverted)
118 - 0x7004: LSB I2C write data bit (inverted)
119 - 0x7008: LSB I2C read clock bit
120 - 0x700c: LSB I2C read data bit
121 - 0x9008: GPIO get input state
122 - 0x900c: GPIO set output state
123 - 0x9020: GPIO direction (Bit7 (GPIO 0..7) - 0:input, 1:output)
124 - 0x9050: SPU control
125 - 0x9054: Reset HW blocks
126 - 0x9058: VPU control
127 - 0xA018: Bit6: interrupt pending?
128 - 0xA064: APU command
131 Interrupt Status Register
132 ~~~~~~~~~~~~~~~~~~~~~~~~~
134 The definition of the bits in the interrupt status register 0x0040, and the
135 interrupt mask 0x0048. If a bit is cleared in the mask, then we want our ISR to
138 - bit 31 Encoder Start Capture
140 - bit 29 Encoder VBI capture
141 - bit 28 Encoder Video Input Module reset event
142 - bit 27 Encoder DMA complete
143 - bit 24 Decoder audio mode change detection event (through event notification)
144 - bit 22 Decoder data request
145 - bit 20 Decoder DMA complete
146 - bit 19 Decoder VBI re-insertion
147 - bit 18 Decoder DMA err (linked-list bad)
149 Missing documentation
150 ---------------------
152 - Encoder API post(?)
153 - Decoder API post(?)
154 - Decoder VTRACE event
157 The cx2341x firmware upload
158 ---------------------------
160 This document describes how to upload the cx2341x firmware to the card.
165 See the web pages of the various projects that uses this chip for information
166 on how to obtain the firmware.
168 The firmware stored in a Windows driver can be detected as follows:
170 - Each firmware image is 256k bytes.
171 - The 1st 32-bit word of the Encoder image is 0x0000da7
172 - The 1st 32-bit word of the Decoder image is 0x00003a7
173 - The 2nd 32-bit word of both images is 0xaa55bb66
178 - Issue the FWapi command to stop the encoder if it is running. Wait for the
180 - Issue the FWapi command to stop the decoder if it is running. Wait for the
182 - Issue the I2C command to the digitizer to stop emitting VSYNC events.
183 - Issue the FWapi command to halt the encoder's firmware.
185 - Issue the FWapi command to halt the decoder's firmware.
187 - Write 0x00000000 to register 0x2800 to stop the Video Display Module.
188 - Write 0x00000005 to register 0x2D00 to stop the AO (audio output?).
189 - Write 0x00000000 to register 0xA064 to ping? the APU.
190 - Write 0xFFFFFFFE to register 0x9058 to stop the VPU.
191 - Write 0xFFFFFFFF to register 0x9054 to reset the HW blocks.
192 - Write 0x00000001 to register 0x9050 to stop the SPU.
194 - Write 0x0000001A to register 0x07FC to init the Encoder SDRAM's pre-charge.
195 - Write 0x80000640 to register 0x07F8 to init the Encoder SDRAM's refresh to 1us.
196 - Write 0x0000001A to register 0x08FC to init the Decoder SDRAM's pre-charge.
197 - Write 0x80000640 to register 0x08F8 to init the Decoder SDRAM's refresh to 1us.
198 - Sleep for 512ms. (600ms is recommended)
199 - Transfer the encoder's firmware image to offset 0 in Encoder memory space.
200 - Transfer the decoder's firmware image to offset 0 in Decoder memory space.
201 - Use a read-modify-write operation to Clear bit 0 of register 0x9050 to
203 - Sleep for 1 second.
204 - Use a read-modify-write operation to Clear bits 3 and 0 of register 0x9058
205 to re-enable the VPU.
206 - Sleep for 1 second.
207 - Issue status API commands to both firmware images to verify.
210 How to call the firmware API
211 ----------------------------
213 The preferred calling convention is known as the firmware mailbox. The
214 mailboxes are basically a fixed length array that serves as the call-stack.
216 Firmware mailboxes can be located by searching the encoder and decoder memory
217 for a 16 byte signature. That signature will be located on a 256-byte boundary.
223 0x78, 0x56, 0x34, 0x12, 0x12, 0x78, 0x56, 0x34,
224 0x34, 0x12, 0x78, 0x56, 0x56, 0x34, 0x12, 0x78
226 The firmware implements 20 mailboxes of 20 32-bit words. The first 10 are
227 reserved for API calls. The second 10 are used by the firmware for event
230 ====== =================
232 ====== =================
237 4-19 Parameter/Result
238 ====== =================
241 The flags are defined in the following table. The direction is from the
242 perspective of the firmware.
244 ==== ========== ============================================
245 Bit Direction Purpose
246 ==== ========== ============================================
247 2 O Firmware has processed the command.
248 1 I Driver has finished setting the parameters.
249 0 I Driver is using this mailbox.
250 ==== ========== ============================================
252 The command is a 32-bit enumerator. The API specifics may be found in this
255 The return value is a 32-bit enumerator. Only two values are currently defined:
258 - -1=command undefined.
260 There are 16 parameters/results 32-bit fields. The driver populates these fields
261 with values for all the parameters required by the call. The driver overwrites
262 these fields with result values returned by the call.
264 The timeout value protects the card from a hung driver thread. If the driver
265 doesn't handle the completed call within the timeout specified, the firmware
266 will reset that mailbox.
268 To make an API call, the driver iterates over each mailbox looking for the
269 first one available (bit 0 has been cleared). The driver sets that bit, fills
270 in the command enumerator, the timeout value and any required parameters. The
271 driver then sets the parameter ready bit (bit 1). The firmware scans the
272 mailboxes for pending commands, processes them, sets the result code, populates
273 the result value array with that call's return values and sets the call
274 complete bit (bit 2). Once bit 2 is set, the driver should retrieve the results
275 and clear all the flags. If the driver does not perform this task within the
276 time set in the timeout register, the firmware will reset that mailbox.
278 Event notifications are sent from the firmware to the host. The host tells the
279 firmware which events it is interested in via an API call. That call tells the
280 firmware which notification mailbox to use. The firmware signals the host via
281 an interrupt. Only the 16 Results fields are used, the Flags, Command, Return
282 value and Timeout words are not used.
285 OSD firmware API description
286 ----------------------------
288 .. note:: this API is part of the decoder firmware, so it's cx23415 only.
292 CX2341X_OSD_GET_FRAMEBUFFER
293 ~~~~~~~~~~~~~~~~~~~~~~~~~~~
300 Return base and length of contiguous OSD memory.
314 CX2341X_OSD_GET_PIXEL_FORMAT
315 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
335 CX2341X_OSD_SET_PIXEL_FORMAT
336 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
350 - 2=16bit ARGB 1:5:5:5
351 - 3=16bit ARGB 1:4:4:4
352 - 4=32bit ARGB 8:8:8:8
356 CX2341X_OSD_GET_STATE
357 ~~~~~~~~~~~~~~~~~~~~~
370 - Bits 1:2 alpha control
371 - Bits 3:5 pixel format
375 CX2341X_OSD_SET_STATE
376 ~~~~~~~~~~~~~~~~~~~~~
392 CX2341X_OSD_GET_OSD_COORDS
393 ~~~~~~~~~~~~~~~~~~~~~~~~~~
400 Retrieve coordinates of OSD area blended with video
420 Horizontal offset in buffer
425 Vertical offset in buffer
429 CX2341X_OSD_SET_OSD_COORDS
430 ~~~~~~~~~~~~~~~~~~~~~~~~~~
437 Assign the coordinates of the OSD area to blend with video
447 buffer stride in pixels
466 CX2341X_OSD_GET_SCREEN_COORDS
467 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
474 Retrieve OSD screen area coordinates
479 top left horizontal offset
484 top left vertical offset
489 bottom right horizontal offset
494 bottom right vertical offset
498 CX2341X_OSD_SET_SCREEN_COORDS
499 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
506 Assign the coordinates of the screen area to blend with video
511 top left horizontal offset
516 top left vertical offset
521 bottom left horizontal offset
526 bottom left vertical offset
530 CX2341X_OSD_GET_GLOBAL_ALPHA
531 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
538 Retrieve OSD global alpha
543 global alpha: 0=off, 1=on
548 bits 0:7 global alpha
552 CX2341X_OSD_SET_GLOBAL_ALPHA
553 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
565 global alpha: 0=off, 1=on
570 global alpha (8 bits)
575 local alpha: 0=on, 1=off
579 CX2341X_OSD_SET_BLEND_COORDS
580 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
587 Move start of blending area within display buffer
592 horizontal offset in buffer
597 vertical offset in buffer
601 CX2341X_OSD_GET_FLICKER_STATE
602 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
609 Retrieve flicker reduction module state
614 flicker state: 0=off, 1=on
618 CX2341X_OSD_SET_FLICKER_STATE
619 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
626 Set flicker reduction module state
651 '0001' ~destination AND ~source
652 '0010' ~destination AND source
654 '0100' destination AND ~source
656 '0110' destination XOR source
657 '0111' ~destination OR ~source
658 '1000' ~destination AND ~source
659 '1001' destination XNOR source
661 '1011' ~destination OR source
663 '1101' destination OR ~source
664 '1110' destination OR source
671 Resulting alpha blending
674 - '10' destination_alpha
675 - '11' source_alpha*destination_alpha+1
676 (zero if both source and destination alpha are zero)
683 '00' output_pixel = source_pixel
685 '01' if source_alpha=0:
686 output_pixel = destination_pixel
687 if 256 > source_alpha > 1:
688 output_pixel = ((source_alpha + 1)*source_pixel +
689 (255 - source_alpha)*destination_pixel)/256
691 '10' if destination_alpha=0:
692 output_pixel = source_pixel
693 if 255 > destination_alpha > 0:
694 output_pixel = ((255 - destination_alpha)*source_pixel +
695 (destination_alpha + 1)*destination_pixel)/256
697 '11' if source_alpha=0:
700 source_temp = source_pixel*256
701 if 255 > source_alpha > 0:
702 source_temp = source_pixel*(source_alpha + 1)
703 if destination_alpha=0:
705 if destination_alpha=255:
706 destination_temp = destination_pixel*256
707 if 255 > destination_alpha > 0:
708 destination_temp = destination_pixel*(destination_alpha + 1)
709 output_pixel = (source_temp + destination_temp)/256
724 destination pixel mask
729 destination rectangle start address
734 destination stride in dwords
739 source stride in dwords
744 source rectangle start address
761 Same as Param[0] on API 0x52
766 Same as Param[1] on API 0x52
771 Same as Param[2] on API 0x52
786 destination pixel mask
791 destination rectangle start address
796 destination stride in dwords
813 BLT for 8 bit alpha text source
818 Same as Param[0] on API 0x52
823 Same as Param[1] on API 0x52
828 Same as Param[2] on API 0x52
843 destination pixel mask
848 destination rectangle start address
853 destination stride in dwords
858 source stride in dwords
863 source rectangle start address
872 CX2341X_OSD_SET_FRAMEBUFFER_WINDOW
873 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
880 Positions the main output window on the screen. The coordinates must be
881 such that the entire window fits on the screen.
896 top left window corner horizontal offset
901 top left window corner vertical offset
905 CX2341X_OSD_SET_CHROMA_KEY
906 ~~~~~~~~~~~~~~~~~~~~~~~~~~
913 Chroma key switch and color
927 CX2341X_OSD_GET_ALPHA_CONTENT_INDEX
928 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
935 Retrieve alpha content index
940 alpha content index, Range 0:15
944 CX2341X_OSD_SET_ALPHA_CONTENT_INDEX
945 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
952 Assign alpha content index
957 alpha content index, range 0:15
960 Encoder firmware API description
961 --------------------------------
971 Does nothing. Can be used to check if the firmware is responding.
975 CX2341X_ENC_START_CAPTURE
976 ~~~~~~~~~~~~~~~~~~~~~~~~~
983 Commences the capture of video, audio and/or VBI data. All encoding
984 parameters must be initialized prior to this API call. Captures frames
985 continuously or until a predefined number of frames have been captured.
1003 - Bit 0 when set, captures YUV
1004 - Bit 1 when set, captures PCM audio
1005 - Bit 2 when set, captures VBI (same as param[0]=3)
1006 - Bit 3 when set, the capture destination is the decoder
1007 (same as param[0]=2)
1008 - Bit 4 when set, the capture destination is the host
1010 .. note:: this parameter is only meaningful for RAW capture type.
1014 CX2341X_ENC_STOP_CAPTURE
1015 ~~~~~~~~~~~~~~~~~~~~~~~~
1022 Ends a capture in progress
1027 - 0=stop at end of GOP (generates IRQ)
1028 - 1=stop immediate (no IRQ)
1033 Stream type to stop, see param[0] of API 0x81
1038 Subtype, see param[1] of API 0x81
1042 CX2341X_ENC_SET_AUDIO_ID
1043 ~~~~~~~~~~~~~~~~~~~~~~~~
1050 Assigns the transport stream ID of the encoded audio stream
1059 CX2341X_ENC_SET_VIDEO_ID
1060 ~~~~~~~~~~~~~~~~~~~~~~~~
1067 Set video transport stream ID
1076 CX2341X_ENC_SET_PCR_ID
1077 ~~~~~~~~~~~~~~~~~~~~~~
1084 Assigns the transport stream ID for PCR packets
1093 CX2341X_ENC_SET_FRAME_RATE
1094 ~~~~~~~~~~~~~~~~~~~~~~~~~~
1101 Set video frames per second. Change occurs at start of new GOP.
1111 CX2341X_ENC_SET_FRAME_SIZE
1112 ~~~~~~~~~~~~~~~~~~~~~~~~~~
1119 Select video stream encoding resolution.
1124 Height in lines. Default 480
1129 Width in pixels. Default 720
1133 CX2341X_ENC_SET_BIT_RATE
1134 ~~~~~~~~~~~~~~~~~~~~~~~~
1141 Assign average video stream bitrate.
1146 0=variable bitrate, 1=constant bitrate
1151 bitrate in bits per second
1156 peak bitrate in bits per second, divided by 400
1161 Mux bitrate in bits per second, divided by 400. May be 0 (default).
1166 Rate Control VBR Padding
1171 VBV Buffer used by encoder
1175 #) Param\[3\] and Param\[4\] seem to be always 0
1176 #) Param\[5\] doesn't seem to be used.
1180 CX2341X_ENC_SET_GOP_PROPERTIES
1181 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1188 Setup the GOP structure
1193 GOP size (maximum is 34)
1198 Number of B frames between the I and P frame, plus 1.
1199 For example: IBBPBBPBBPBB --> GOP size: 12, number of B frames: 2+1 = 3
1203 GOP size must be a multiple of (B-frames + 1).
1207 CX2341X_ENC_SET_ASPECT_RATIO
1208 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1215 Sets the encoding aspect ratio. Changes in the aspect ratio take effect
1216 at the start of the next GOP.
1226 - '0101' to '1111' reserved
1230 CX2341X_ENC_SET_DNR_FILTER_MODE
1231 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1238 Assign Dynamic Noise Reduction operating mode
1243 Bit0: Spatial filter, set=auto, clear=manual
1244 Bit1: Temporal filter, set=auto, clear=manual
1259 CX2341X_ENC_SET_DNR_FILTER_PROPS
1260 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1267 These Dynamic Noise Reduction filter values are only meaningful when
1268 the respective filter is set to "manual" (See API 0x9B)
1273 Spatial filter: default 0, range 0:15
1278 Temporal filter: default 0, range 0:31
1282 CX2341X_ENC_SET_CORING_LEVELS
1283 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1290 Assign Dynamic Noise Reduction median filter properties.
1295 Threshold above which the luminance median filter is enabled.
1296 Default: 0, range 0:255
1301 Threshold below which the luminance median filter is enabled.
1302 Default: 255, range 0:255
1307 Threshold above which the chrominance median filter is enabled.
1308 Default: 0, range 0:255
1313 Threshold below which the chrominance median filter is enabled.
1314 Default: 255, range 0:255
1318 CX2341X_ENC_SET_SPATIAL_FILTER_TYPE
1319 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1326 Assign spatial prefilter parameters
1336 - 3=2D H/V Separable (default)
1337 - 4=2D Symmetric non-separable
1345 - 1=1D Horizontal (default)
1349 CX2341X_ENC_SET_VBI_LINE
1350 ~~~~~~~~~~~~~~~~~~~~~~~~
1357 Selects VBI line number.
1362 - Bits 0:4 line number
1363 - Bit 31 0=top_field, 1=bottom_field
1364 - Bits 0:31 all set specifies "all lines"
1369 VBI line information features: 0=disabled, 1=enabled
1374 Slicing: 0=None, 1=Closed Caption
1375 Almost certainly not implemented. Set to 0.
1380 Luminance samples in this line.
1381 Almost certainly not implemented. Set to 0.
1386 Chrominance samples in this line
1387 Almost certainly not implemented. Set to 0.
1391 CX2341X_ENC_SET_STREAM_TYPE
1392 ~~~~~~~~~~~~~~~~~~~~~~~~~~~
1403 Transport stream is not working in recent firmwares.
1404 And in older firmwares the timestamps in the TS seem to be
1411 - 1=Transport stream
1414 - 5=PES Video stream
1415 - 7=PES Audio stream
1424 CX2341X_ENC_SET_OUTPUT_PORT
1425 ~~~~~~~~~~~~~~~~~~~~~~~~~~~
1432 Assign stream output port. Normally 0 when the data is copied through
1433 the PCI bus (DMA), and 1 when the data is streamed to another chip
1434 (pvrusb and cx88-blackbird).
1439 - 0=Memory (default)
1446 Unknown, but leaving this to 0 seems to work best. Indications are that
1447 this might have to do with USB support, although passing anything but 0
1452 CX2341X_ENC_SET_AUDIO_PROPERTIES
1453 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1460 Set audio stream properties, may be called while encoding is in progress.
1464 All bitfields are consistent with ISO11172 documentation except
1465 bits 2:3 which ISO docs define as:
1472 This discrepancy may indicate a possible error in the documentation.
1473 Testing indicated that only Layer II is actually working, and that
1474 the minimum bitrate should be 192 kbps.
1481 .. code-block:: none
1492 Index | Layer I | Layer II
1493 ------+-------------+------------
1494 '0000' | free format | free format
1495 '0001' | 32 kbit/s | 32 kbit/s
1496 '0010' | 64 kbit/s | 48 kbit/s
1497 '0011' | 96 kbit/s | 56 kbit/s
1498 '0100' | 128 kbit/s | 64 kbit/s
1499 '0101' | 160 kbit/s | 80 kbit/s
1500 '0110' | 192 kbit/s | 96 kbit/s
1501 '0111' | 224 kbit/s | 112 kbit/s
1502 '1000' | 256 kbit/s | 128 kbit/s
1503 '1001' | 288 kbit/s | 160 kbit/s
1504 '1010' | 320 kbit/s | 192 kbit/s
1505 '1011' | 352 kbit/s | 224 kbit/s
1506 '1100' | 384 kbit/s | 256 kbit/s
1507 '1101' | 416 kbit/s | 320 kbit/s
1508 '1110' | 448 kbit/s | 384 kbit/s
1512 For Layer II, not all combinations of total bitrate
1513 and mode are allowed. See ISO11172-3 3-Annex B,
1523 The cx23415 cannot decode Joint Stereo properly.
1525 10:11 Mode Extension used in joint_stereo mode.
1526 In Layer I and II they indicate which subbands are in
1527 intensity_stereo. All other subbands are coded in stereo.
1528 '00' subbands 4-31 in intensity_stereo, bound==4
1529 '01' subbands 8-31 in intensity_stereo, bound==8
1530 '10' subbands 12-31 in intensity_stereo, bound==12
1531 '11' subbands 16-31 in intensity_stereo, bound==16
1561 The firmware is halted and no further API calls are serviced until the
1562 firmware is uploaded again.
1566 CX2341X_ENC_GET_VERSION
1567 ~~~~~~~~~~~~~~~~~~~~~~~
1574 Returns the version of the encoder firmware.
1586 CX2341X_ENC_SET_GOP_CLOSURE
1587 ~~~~~~~~~~~~~~~~~~~~~~~~~~~
1594 Assigns the GOP open/close property.
1604 CX2341X_ENC_GET_SEQ_END
1605 ~~~~~~~~~~~~~~~~~~~~~~~
1612 Obtains the sequence end code of the encoder's buffer. When a capture
1613 is started a number of interrupts are still generated, the last of
1614 which will have Result[0] set to 1 and Result[1] will contain the size
1620 State of the transfer (1 if last buffer)
1625 If Result[0] is 1, this contains the size of the last buffer, undefined
1630 CX2341X_ENC_SET_PGM_INDEX_INFO
1631 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1638 Sets the Program Index Information.
1639 The information is stored as follows:
1644 u32 length; // Length of this frame
1645 u32 offset_low; // Offset in the file of the
1646 u32 offset_high; // start of this frame
1647 u32 mask1; // Bits 0-2 are the type mask:
1649 // 0=End of Program Index, other fields
1651 u32 pts; // The PTS of the frame
1652 u32 mask2; // Bit 0 is bit 32 of the pts.
1655 struct info index[400];
1657 The table_ptr is the encoder memory address in the table were
1658 *new* entries will be written.
1660 .. note:: This is a ringbuffer, so the table_ptr will wraparound.
1666 - 0=No index capture
1671 (Seems to be ignored, it always indexes I, P and B frames)
1676 Elements requested (up to 400)
1681 Offset in the encoder memory of the start of the table.
1686 Number of allocated elements up to a maximum of Param[1]
1690 CX2341X_ENC_SET_VBI_CONFIG
1691 ~~~~~~~~~~~~~~~~~~~~~~~~~~
1698 Configure VBI settings
1705 .. code-block:: none
1707 0 Mode '0' Sliced, '1' Raw
1709 '000' insert in extension & user data
1710 '001' insert in private packets
1711 '010' separate stream and user data
1712 '111' separate stream and private data
1713 8:15 Stream ID (normally 0xBD)
1718 Frames per interrupt (max 8). Only valid in raw mode.
1723 Total raw VBI frames. Only valid in raw mode.
1748 Observed frames per interrupt in raw mode only. Rage 1 to Param[1]
1753 Observed number of frames in raw mode. Range 1 to Param[2]
1758 Memory offset to start or raw VBI data
1762 CX2341X_ENC_SET_DMA_BLOCK_SIZE
1763 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1770 Set DMA transfer block size
1775 DMA transfer block size in bytes or frames. When unit is bytes,
1776 supported block sizes are 2^7, 2^8 and 2^9 bytes.
1781 Unit: 0=bytes, 1=frames
1785 CX2341X_ENC_GET_PREV_DMA_INFO_MB_10
1786 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1793 Returns information on the previous DMA transfer in conjunction with
1794 bit 27 of the interrupt mask. Uses mailbox 10.
1809 Maximum size of transfer
1813 CX2341X_ENC_GET_PREV_DMA_INFO_MB_9
1814 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1821 Returns information on the previous DMA transfer in conjunction with
1822 bit 27 or 18 of the interrupt mask. Uses mailbox 9.
1832 - 4 Scatter-Gather array error
1842 Presentation Time Stamp bits 0..31
1847 Presentation Time Stamp bit 32
1851 CX2341X_ENC_SCHED_DMA_TO_HOST
1852 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1859 Setup DMA to host operation
1864 Memory address of link list
1869 Length of link list (wtf: what units ???)
1878 CX2341X_ENC_INITIALIZE_INPUT
1879 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1886 Initializes the video input
1890 CX2341X_ENC_SET_FRAME_DROP_RATE
1891 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1898 For each frame captured, skip specified number of frames.
1903 Number of frames to skip
1907 CX2341X_ENC_PAUSE_ENCODER
1908 ~~~~~~~~~~~~~~~~~~~~~~~~~
1915 During a pause condition, all frames are dropped instead of being encoded.
1921 - 1=Continue encoding
1925 CX2341X_ENC_REFRESH_INPUT
1926 ~~~~~~~~~~~~~~~~~~~~~~~~~
1933 Refreshes the video input
1937 CX2341X_ENC_SET_COPYRIGHT
1938 ~~~~~~~~~~~~~~~~~~~~~~~~~
1945 Sets stream copyright property
1951 - 0=Stream is not copyrighted
1952 - 1=Stream is copyrighted
1956 CX2341X_ENC_SET_EVENT_NOTIFICATION
1957 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1964 Setup firmware to notify the host about a particular event. Host must
1965 unmask the interrupt bit.
1970 Event (0=refresh encoder input)
1975 Notification 0=disabled 1=enabled
1985 Mailbox slot, -1 if no mailbox required.
1989 CX2341X_ENC_SET_NUM_VSYNC_LINES
1990 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1997 Depending on the analog video decoder used, this assigns the number
1998 of lines for field 1 and 2.
2003 Field 1 number of lines:
2004 - 0x00EF for SAA7114
2005 - 0x00F0 for SAA7115
2006 - 0x0105 for Micronas
2011 Field 2 number of lines:
2012 - 0x00EF for SAA7114
2013 - 0x00F0 for SAA7115
2014 - 0x0106 for Micronas
2018 CX2341X_ENC_SET_PLACEHOLDER
2019 ~~~~~~~~~~~~~~~~~~~~~~~~~~~
2026 Provides a mechanism of inserting custom user data in the MPEG stream.
2031 - 0=extension & user data
2032 - 1=private packet with stream ID 0xBD
2037 Rate at which to insert data, in units of frames (for private packet)
2038 or GOPs (for ext. & user data)
2043 Number of data DWORDs (below) to insert
2092 CX2341X_ENC_MUTE_VIDEO
2093 ~~~~~~~~~~~~~~~~~~~~~~
2107 .. code-block:: none
2109 0 '0'=video not muted
2110 '1'=video muted, creates frames with the YUV color defined below
2112 8:15 V chrominance information
2113 16:23 U chrominance information
2114 24:31 Y luminance information
2118 CX2341X_ENC_MUTE_AUDIO
2119 ~~~~~~~~~~~~~~~~~~~~~~
2132 - 1=audio muted (produces silent mpeg audio stream)
2136 CX2341X_ENC_SET_VERT_CROP_LINE
2137 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2144 Something to do with 'Vertical Crop Line'
2149 If saa7114 and raw VBI capture and 60 Hz, then set to 10001.
2162 Miscellaneous actions. Not known for 100% what it does. It's really a
2163 sort of ioctl call. The first parameter is a command number, the second
2171 .. code-block:: none
2173 1=set initial SCR value when starting encoding (works).
2174 2=set quality mode (apparently some test setting).
2175 3=setup advanced VIM protection handling.
2176 Always 1 for the cx23416 and 0 for cx23415.
2177 4=generate DVD compatible PTS timestamps
2179 6=something to do with the quantization matrix
2180 7=set navigation pack insertion for DVD: adds 0xbf (private stream 2)
2181 packets to the MPEG. The size of these packets is 2048 bytes (including
2182 the header of 6 bytes: 0x000001bf + length). The payload is zeroed and
2183 it is up to the application to fill them in. These packets are apparently
2184 inserted every four frames.
2185 8=enable scene change detection (seems to be a failure)
2186 9=set history parameters of the video input module
2187 10=set input field order of VIM
2188 11=set quantization matrix
2189 12=reset audio interface after channel change or input switch (has no argument).
2190 Needed for the cx2584x, not needed for the mspx4xx, but it doesn't seem to
2191 do any harm calling it regardless.
2192 13=set audio volume delay
2201 Decoder firmware API description
2202 --------------------------------
2204 .. note:: this API is part of the decoder firmware, so it's cx23415 only.
2216 This API call does nothing. It may be used to check if the firmware
2221 CX2341X_DEC_START_PLAYBACK
2222 ~~~~~~~~~~~~~~~~~~~~~~~~~~
2229 Begin or resume playback.
2234 0 based frame number in GOP to begin playback from.
2239 Specifies the number of muted audio frames to play before normal
2240 audio resumes. (This is not implemented in the firmware, leave at 0)
2244 CX2341X_DEC_STOP_PLAYBACK
2245 ~~~~~~~~~~~~~~~~~~~~~~~~~
2252 Ends playback and clears all decoder buffers. If PTS is not zero,
2253 playback stops at specified PTS.
2258 Display 0=last frame, 1=black
2262 this takes effect immediately, so if you want to wait for a PTS,
2263 then use '0', otherwise the screen goes to black at once.
2264 You can call this later (even if there is no playback) with a 1 value
2265 to set the screen to black.
2279 CX2341X_DEC_SET_PLAYBACK_SPEED
2280 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2287 Playback stream at speed other than normal. There are two modes of
2290 - Smooth: host transfers entire stream and firmware drops unused
2292 - Coarse: host drops frames based on indexing as required to achieve
2298 .. code-block:: none
2302 1 fast only "1.5 times"
2303 n nX fast, 1/nX slow
2305 '0' during 1.5 times play, every other B frame is dropped
2306 '1' during 1.5 times play, stream is unchanged (bitrate
2307 must not exceed 8mbps)
2314 n is limited to 2. Anything higher does not result in
2315 faster playback. Instead the host should start dropping frames.
2320 Direction: 0=forward, 1=reverse
2324 to make reverse playback work you have to write full GOPs in
2330 .. code-block:: none
2340 B frames per GOP (for reverse play only)
2344 for reverse playback the Picture Mask should be set to I or I, P.
2345 Adding B frames to the mask will result in corrupt video. This field
2346 has to be set to the correct value in order to keep the timing correct.
2351 Mute audio: 0=disable, 1=enable
2356 Display 0=frame, 1=field
2361 Specifies the number of muted audio frames to play before normal audio
2362 resumes. (Not implemented in the firmware, leave at 0)
2366 CX2341X_DEC_STEP_VIDEO
2367 ~~~~~~~~~~~~~~~~~~~~~~
2374 Each call to this API steps the playback to the next unit defined below
2375 in the current playback direction.
2380 0=frame, 1=top field, 2=bottom field
2384 CX2341X_DEC_SET_DMA_BLOCK_SIZE
2385 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2392 Set DMA transfer block size. Counterpart to API 0xC9
2397 DMA transfer block size in bytes. A different size may be specified
2398 when issuing the DMA transfer command.
2402 CX2341X_DEC_GET_XFER_INFO
2403 ~~~~~~~~~~~~~~~~~~~~~~~~~
2410 This API call may be used to detect an end of stream condition.
2425 Maximum bytes to transfer
2434 CX2341X_DEC_GET_DMA_STATUS
2435 ~~~~~~~~~~~~~~~~~~~~~~~~~~
2442 Status of the last DMA transfer
2447 Bit 1 set means transfer complete
2448 Bit 2 set means DMA error
2449 Bit 3 set means linked list error
2454 DMA type: 0=MPEG, 1=OSD, 2=YUV
2458 CX2341X_DEC_SCHED_DMA_FROM_HOST
2459 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2466 Setup DMA from host operation. Counterpart to API 0xCC
2471 Memory address of link list
2476 Total # of bytes to transfer
2481 DMA type (0=MPEG, 1=OSD, 2=YUV)
2485 CX2341X_DEC_PAUSE_PLAYBACK
2486 ~~~~~~~~~~~~~~~~~~~~~~~~~~
2493 Freeze playback immediately. In this mode, when internal buffers are
2494 full, no more data will be accepted and data request IRQs will be
2500 Display: 0=last frame, 1=black
2512 The firmware is halted and no further API calls are serviced until
2513 the firmware is uploaded again.
2517 CX2341X_DEC_SET_STANDARD
2518 ~~~~~~~~~~~~~~~~~~~~~~~~
2525 Selects display standard
2534 CX2341X_DEC_GET_VERSION
2535 ~~~~~~~~~~~~~~~~~~~~~~~
2542 Returns decoder firmware version information
2554 CX2341X_DEC_SET_STREAM_INPUT
2555 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2562 Select decoder stream input port
2567 0=memory (default), 1=streaming
2571 CX2341X_DEC_GET_TIMING_INFO
2572 ~~~~~~~~~~~~~~~~~~~~~~~~~~~
2579 Returns timing information from start of playback
2584 Frame count by decode order
2589 Video PTS bits 0:31 by display order
2594 Video PTS bit 32 by display order
2599 SCR bits 0:31 by display order
2604 SCR bit 32 by display order
2608 CX2341X_DEC_SET_AUDIO_MODE
2609 ~~~~~~~~~~~~~~~~~~~~~~~~~~
2621 Dual mono mode action
2622 0=Stereo, 1=Left, 2=Right, 3=Mono, 4=Swap, -1=Unchanged
2628 0=Stereo, 1=Left, 2=Right, 3=Mono, 4=Swap, -1=Unchanged
2632 CX2341X_DEC_SET_EVENT_NOTIFICATION
2633 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2640 Setup firmware to notify the host about a particular event.
2641 Counterpart to API 0xD5
2647 - 0=Audio mode change between mono, (joint) stereo and dual channel.
2649 - 4=Unknown: goes off 10-15 times per second while decoding.
2650 - 5=Some sync event: goes off once per frame.
2655 Notification 0=disabled, 1=enabled
2665 Mailbox slot, -1 if no mailbox required.
2669 CX2341X_DEC_SET_DISPLAY_BUFFERS
2670 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2677 Number of display buffers. To decode all frames in reverse playback you
2678 must use nine buffers.
2683 0=six buffers, 1=nine buffers
2687 CX2341X_DEC_EXTRACT_VBI
2688 ~~~~~~~~~~~~~~~~~~~~~~~
2700 0=extract from extension & user data, 1=extract from private packets
2714 CX2341X_DEC_SET_DECODER_SOURCE
2715 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2722 Selects decoder source. Ensure that the parameters passed to this
2723 API match the encoder settings.
2728 Mode: 0=MPEG from host, 1=YUV from encoder, 2=YUV from host
2743 Bitmap: see Param[0] of API 0xBD
2747 CX2341X_DEC_SET_PREBUFFERING
2748 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2755 Decoder prebuffering, when enabled up to 128KB are buffered for
2756 streams <8mpbs or 640KB for streams >8mbps
2763 PVR350 Video decoder registers 0x02002800 -> 0x02002B00
2764 -------------------------------------------------------
2766 Author: Ian Armstrong <ian@iarmst.demon.co.uk>
2773 This list has been worked out through trial and error. There will be mistakes
2774 and omissions. Some registers have no obvious effect so it's hard to say what
2775 they do, while others interact with each other, or require a certain load
2776 sequence. Horizontal filter setup is one example, with six registers working
2777 in unison and requiring a certain load sequence to correctly configure. The
2778 indexed colour palette is much easier to set at just two registers, but again
2779 it requires a certain load sequence.
2781 Some registers are fussy about what they are set to. Load in a bad value & the
2782 decoder will fail. A firmware reload will often recover, but sometimes a reset
2783 is required. For registers containing size information, setting them to 0 is
2784 generally a bad idea. For other control registers i.e. 2878, you'll only find
2785 out what values are bad when it hangs.
2787 .. code-block:: none
2789 --------------------------------------------------------------------------------
2795 --------------------------------------------------------------------------------
2798 Decoder horizontal Y alias register 1
2802 Decoder horizontal Y alias register 2
2806 Decoder horizontal Y alias register 3
2810 Decoder horizontal Y alias register 4
2814 Decoder horizontal Y alias register 5
2818 Decoder horizontal Y alias trigger
2820 These six registers control the horizontal aliasing filter for the Y plane.
2821 The first five registers must all be loaded before accessing the trigger
2822 (2818), as this register actually clocks the data through for the first
2825 To correctly program set the filter, this whole procedure must be done 16
2826 times. The actual register contents are copied from a lookup-table in the
2827 firmware which contains 4 different filter settings.
2829 --------------------------------------------------------------------------------
2832 Decoder horizontal UV alias register 1
2836 Decoder horizontal UV alias register 2
2840 Decoder horizontal UV alias register 3
2844 Decoder horizontal UV alias register 4
2848 Decoder horizontal UV alias register 5
2852 Decoder horizontal UV alias trigger
2854 These six registers control the horizontal aliasing for the UV plane.
2855 Operation is the same as the Y filter, with 2830 being the trigger
2858 --------------------------------------------------------------------------------
2861 Decoder Y source width in pixels
2864 Decoder Y destination width in pixels
2868 Decoder UV source width in pixels
2871 Decoder UV destination width in pixels
2873 NOTE: For both registers, the resulting image must be fully visible on
2874 screen. If the image exceeds the right edge both the source and destination
2875 size must be adjusted to reflect the visible portion. For the source width,
2876 you must take into account the scaling when calculating the new value.
2877 --------------------------------------------------------------------------------
2881 Decoder Y horizontal scaling
2882 Normally = Reg 2854 >> 2
2886 Decoder ?? unknown - horizontal scaling
2891 Decoder UV horizontal scaling
2892 Normally = Reg 2854 >> 2
2896 Decoder ?? unknown - horizontal scaling
2901 Decoder ?? unknown - Y plane
2906 Decoder ?? unknown - UV plane
2911 Decoder 'master' value for horizontal scaling
2921 Normally = Reg 2854 >> 1
2931 Normally = Reg 2854 >> 1
2938 Most of these registers either control horizontal scaling, or appear linked
2939 to it in some way. Register 2854 contains the 'master' value & the other
2940 registers can be calculated from that one. You must also remember to
2941 correctly set the divider in Reg 2874.
2944 Reg 2854 = (source_width * 0x00200000) / destination_width
2945 Reg 2874 = No divide
2947 To reduce from full size down to half size:
2948 Reg 2854 = (source_width/2 * 0x00200000) / destination width
2949 Reg 2874 = Divide by 2
2951 To reduce from half size down to quarter size:
2952 Reg 2854 = (source_width/4 * 0x00200000) / destination width
2953 Reg 2874 = Divide by 4
2955 The result is always rounded up.
2957 --------------------------------------------------------------------------------
2960 Decoder horizontal Y buffer offset
2963 Decoder horizontal UV buffer offset
2965 Offset into the video image buffer. If the offset is gradually incremented,
2966 the on screen image will move left & wrap around higher up on the right.
2968 --------------------------------------------------------------------------------
2971 Decoder horizontal Y output offset
2974 Decoder horizontal UV output offset
2976 Offsets the actual video output. Controls output alignment of the Y & UV
2977 planes. The higher the value, the greater the shift to the left. Use
2978 reg 2890 to move the image right.
2980 --------------------------------------------------------------------------------
2983 Decoder horizontal Y output size divider
2989 Decoder horizontal UV output size divider
2997 1 = Affects video output levels
3002 1 = Disable horizontal filter
3004 --------------------------------------------------------------------------------
3015 Decoder + osd video timing
3024 Swaps upper & lower fields
3026 --------------------------------------------------------------------------------
3029 Decoder & osd ?? unknown
3030 Moves entire screen horizontally. Starts at 0x005 with the screen
3031 shifted heavily to the right. Incrementing in steps of 0x004 will
3032 gradually shift the screen to the left.
3037 Normally contents are 0x00101111 (NTSC) or 0x1010111d (PAL)
3039 --------------------------------------------------------------------------------
3040 2880 -------- ?? unknown
3041 2884 -------- ?? unknown
3042 --------------------------------------------------------------------------------
3045 Decoder + osd ?? unknown
3047 1 = Misaligned fields (Correctable through 289C & 28A4)
3055 Warning: Bad values will require a firmware reload to recover.
3056 Known to be bad are 0x000,0x011,0x100,0x111
3057 --------------------------------------------------------------------------------
3061 Appears to affect the osd position stability. The higher the value the
3062 more unstable it becomes. Decoder output remains stable.
3068 --------------------------------------------------------------------------------
3071 Decoder output horizontal offset.
3073 Horizontal offset moves the video image right. A small left shift is
3074 possible, but it's better to use reg 2870 for that due to its greater
3077 NOTE: Video corruption will occur if video window is shifted off the right
3078 edge. To avoid this read the notes for 2834 & 2838.
3079 --------------------------------------------------------------------------------
3082 Decoder output video surround colour.
3084 Contains the colour (in yuv) used to fill the screen when the video is
3085 running in a window.
3086 --------------------------------------------------------------------------------
3089 Decoder video window colour
3090 Contains the colour (in yuv) used to fill the video window when the
3091 video is turned off.
3094 Decoder video output
3104 Decoder second plane byte order
3108 In normal usage, the first plane is Y & the second plane is UV. Though the
3109 order of the planes can be swapped, only the byte order of the second plane
3110 can be swapped. This isn't much use for the Y plane, but can be useful for
3113 --------------------------------------------------------------------------------
3116 Decoder vertical field offset 1
3119 Decoder vertical field offset 2
3121 Controls field output vertical alignment. The higher the number, the lower
3122 the image on screen. Known starting values are 0x011E0017 (NTSC) &
3124 --------------------------------------------------------------------------------
3127 Decoder & osd width in pixels
3130 Decoder & osd height in pixels
3132 All output from the decoder & osd are disabled beyond this area. Decoder
3133 output will simply go black outside of this region. If the osd tries to
3134 exceed this area it will become corrupt.
3135 --------------------------------------------------------------------------------
3140 Has a range of 0x770->0x7FF. With the exception of 0, any value outside of
3141 this range corrupts the osd.
3142 --------------------------------------------------------------------------------
3145 osd vertical field offset 1
3148 osd vertical field offset 2
3150 Controls field output vertical alignment. The higher the number, the lower
3151 the image on screen. Known starting values are 0x011E0017 (NTSC) &
3153 --------------------------------------------------------------------------------
3154 28AC -------- ?? unknown
3157 28BC -------- ?? unknown
3158 --------------------------------------------------------------------------------
3161 Current output field
3167 The scanline counts from the top line of the first field
3168 through to the last line of the second field.
3169 --------------------------------------------------------------------------------
3170 28C4 -------- ?? unknown
3173 28F8 -------- ?? unknown
3174 --------------------------------------------------------------------------------
3179 1 = Breaks decoder & osd output
3180 --------------------------------------------------------------------------------
3183 Decoder vertical Y alias register 1
3187 Decoder vertical Y alias register 2
3191 Decoder vertical Y alias trigger
3193 These three registers control the vertical aliasing filter for the Y plane.
3194 Operation is similar to the horizontal Y filter (2804). The only real
3195 difference is that there are only two registers to set before accessing
3196 the trigger register (2908). As for the horizontal filter, the values are
3197 taken from a lookup table in the firmware, and the procedure must be
3198 repeated 16 times to fully program the filter.
3199 --------------------------------------------------------------------------------
3202 Decoder vertical UV alias register 1
3206 Decoder vertical UV alias register 2
3210 Decoder vertical UV alias trigger
3212 These three registers control the vertical aliasing filter for the UV
3213 plane. Operation is the same as the Y filter, with 2914 being the trigger.
3214 --------------------------------------------------------------------------------
3217 Decoder Y source height in pixels
3220 Decoder Y destination height in pixels
3224 Decoder UV source height in pixels divided by 2
3227 Decoder UV destination height in pixels
3229 NOTE: For both registers, the resulting image must be fully visible on
3230 screen. If the image exceeds the bottom edge both the source and
3231 destination size must be adjusted to reflect the visible portion. For the
3232 source height, you must take into account the scaling when calculating the
3234 --------------------------------------------------------------------------------
3237 Decoder Y vertical scaling
3238 Normally = Reg 2930 >> 2
3242 Decoder Y vertical scaling
3243 Normally = Reg 2920 + 0x514
3247 Decoder UV vertical scaling
3248 When enlarging = Reg 2930 >> 2
3249 When reducing = Reg 2930 >> 3
3253 Decoder UV vertical scaling
3254 Normally = Reg 2928 + 0x514
3258 Decoder 'master' value for vertical scaling
3262 Decoder ?? unknown - Y vertical scaling
3266 Decoder Y vertical scaling
3271 Decoder ?? unknown - Y vertical scaling
3275 Decoder UV vertical scaling
3276 When enlarging = Reg 2930 >> 1
3277 When reducing = Reg 2930
3281 Decoder ?? unknown - UV vertical scaling
3285 Decoder UV vertical scaling
3290 Decoder ?? unknown - UV vertical scaling
3292 Most of these registers either control vertical scaling, or appear linked
3293 to it in some way. Register 2930 contains the 'master' value & all other
3294 registers can be calculated from that one. You must also remember to
3295 correctly set the divider in Reg 296C
3298 Reg 2930 = (source_height * 0x00200000) / destination_height
3299 Reg 296C = No divide
3301 To reduce from full size down to half size:
3302 Reg 2930 = (source_height/2 * 0x00200000) / destination height
3303 Reg 296C = Divide by 2
3305 To reduce from half down to quarter.
3306 Reg 2930 = (source_height/4 * 0x00200000) / destination height
3307 Reg 296C = Divide by 4
3309 --------------------------------------------------------------------------------
3312 Decoder Y line index into display buffer, first field
3315 Decoder Y vertical line skip, first field
3316 --------------------------------------------------------------------------------
3319 Decoder Y line index into display buffer, second field
3322 Decoder Y vertical line skip, second field
3323 --------------------------------------------------------------------------------
3326 Decoder UV line index into display buffer, first field
3329 Decoder UV vertical line skip, first field
3330 --------------------------------------------------------------------------------
3333 Decoder UV line index into display buffer, second field
3336 Decoder UV vertical line skip, second field
3337 --------------------------------------------------------------------------------
3340 Decoder destination height minus 1
3343 Decoder destination height divided by 2
3344 --------------------------------------------------------------------------------
3347 Decoder Y vertical offset, second field
3350 Decoder Y vertical offset, first field
3352 These two registers shift the Y plane up. The higher the number, the
3354 --------------------------------------------------------------------------------
3357 Decoder UV vertical offset, second field
3360 Decoder UV vertical offset, first field
3362 These two registers shift the UV plane up. The higher the number, the
3364 --------------------------------------------------------------------------------
3367 Decoder vertical Y output size divider
3373 Decoder vertical UV output size divider
3377 --------------------------------------------------------------------------------
3382 1 = Affect video output levels
3387 1 = Disable vertical filter
3389 --------------------------------------------------------------------------------
3390 2974 -------- ?? unknown
3393 29EF -------- ?? unknown
3394 --------------------------------------------------------------------------------
3436 Must be 0x001B (some kind of buffer pointer ?)
3438 When the bits-per-pixel is set to 8, the colour mode is ignored and
3439 assumed to be 8 bit indexed. For 16 & 32 bits-per-pixel the colour depth
3440 is honoured, and when using a colour depth that requires fewer bytes than
3441 allocated the extra bytes are used as padding. So for a 32 bpp with 8 bit
3442 index colour, there are 3 padding bytes per pixel. It's also possible to
3443 select 16bpp with a 32 bit colour mode. This results in the pixel width
3444 being doubled, but the color key will not work as expected in this mode.
3446 Colour key is as it suggests. You designate a colour which will become
3447 completely transparent. When using 565, 555 or 444 colour modes, the
3448 colour key is always 16 bits wide. The colour to key on is set in Reg 2A18.
3450 Local alpha works differently depending on the colour mode. For 32bpp & 8
3451 bit indexed, local alpha is a per-pixel 256 step transparency, with 0 being
3452 transparent and 255 being solid. For the 16bpp modes 555 & 444, the unused
3453 bit(s) act as a simple transparency switch, with 0 being solid & 1 being
3454 fully transparent. There is no local alpha support for 16bit 565.
3456 Global alpha is a 256 step transparency that applies to the entire osd,
3457 with 0 being transparent & 255 being solid.
3459 It's possible to combine colour key, local alpha & global alpha.
3460 --------------------------------------------------------------------------------
3463 osd x coord for left edge
3466 osd y coord for top edge
3470 osd x coord for right edge
3473 osd y coord for bottom edge
3475 For both registers, (0,0) = top left corner of the display area. These
3476 registers do not control the osd size, only where it's positioned & how
3477 much is visible. The visible osd area cannot exceed the right edge of the
3478 display, otherwise the osd will become corrupt. See reg 2A10 for
3480 --------------------------------------------------------------------------------
3485 An index into the osd buffer. Slowly incrementing this moves the osd left,
3486 wrapping around onto the right edge
3487 --------------------------------------------------------------------------------
3490 osd buffer 32 bit word width
3492 Contains the width of the osd measured in 32 bit words. This means that all
3493 colour modes are restricted to a byte width which is divisible by 4.
3494 --------------------------------------------------------------------------------
3497 osd height in pixels
3500 osd line index into buffer
3501 osd will start displaying from this line.
3502 --------------------------------------------------------------------------------
3507 Contains the colour value which will be transparent.
3508 --------------------------------------------------------------------------------
3513 Contains the global alpha value (equiv ivtvfbctl --alpha XX)
3514 --------------------------------------------------------------------------------
3515 2A20 -------- ?? unknown
3518 2A2C -------- ?? unknown
3519 --------------------------------------------------------------------------------
3522 osd colour to change in indexed palette
3526 osd colour for indexed palette
3528 To set the new palette, first load the index of the colour to change into
3529 2A30, then load the new colour into 2A34. The full palette is 256 colours,
3530 so the index range is 0x00-0xFF
3531 --------------------------------------------------------------------------------
3532 2A38 -------- ?? unknown
3533 2A3C -------- ?? unknown
3534 --------------------------------------------------------------------------------
3539 Affects overall brightness, wrapping around to black
3540 --------------------------------------------------------------------------------
3546 --------------------------------------------------------------------------------
3552 --------------------------------------------------------------------------------
3557 Affects overall brightness, wrapping around to black
3558 --------------------------------------------------------------------------------
3564 --------------------------------------------------------------------------------
3570 --------------------------------------------------------------------------------
3571 2A58 -------- ?? unknown
3574 2AFC -------- ?? unknown
3575 --------------------------------------------------------------------------------
3585 --------------------------------------------------------------------------------
3587 The cx231xx DMA engine
3588 ----------------------
3591 This page describes the structures and procedures used by the cx2341x DMA
3597 The cx2341x PCI interface is busmaster capable. This means it has a DMA
3598 engine to efficiently transfer large volumes of data between the card and main
3599 memory without requiring help from a CPU. Like most hardware, it must operate
3600 on contiguous physical memory. This is difficult to come by in large quantities
3601 on virtual memory machines.
3603 Therefore, it also supports a technique called "scatter-gather". The card can
3604 transfer multiple buffers in one operation. Instead of allocating one large
3605 contiguous buffer, the driver can allocate several smaller buffers.
3607 In practice, I've seen the average transfer to be roughly 80K, but transfers
3608 above 128K were not uncommon, particularly at startup. The 128K figure is
3609 important, because that is the largest block that the kernel can normally
3610 allocate. Even still, 128K blocks are hard to come by, so the driver writer is
3611 urged to choose a smaller block size and learn the scatter-gather technique.
3613 Mailbox #10 is reserved for DMA transfer information.
3615 Note: the hardware expects little-endian data ('intel format').
3620 This section describes, in general, the order of events when handling DMA
3621 transfers. Detailed information follows this section.
3623 - The card raises the Encoder interrupt.
3624 - The driver reads the transfer type, offset and size from Mailbox #10.
3625 - The driver constructs the scatter-gather array from enough free dma buffers
3627 - The driver schedules the DMA transfer via the ScheduleDMAtoHost API call.
3628 - The card raises the DMA Complete interrupt.
3629 - The driver checks the DMA status register for any errors.
3630 - The driver post-processes the newly transferred buffers.
3632 NOTE! It is possible that the Encoder and DMA Complete interrupts get raised
3633 simultaneously. (End of the last, start of the next, etc.)
3638 The Flags, Command, Return Value and Timeout fields are ignored.
3641 - Results[0]: Type: 0: MPEG.
3642 - Results[1]: Offset: The position relative to the card's memory space.
3643 - Results[2]: Size: The exact number of bytes to transfer.
3645 My speculation is that since the StartCapture API has a capture type of "RAW"
3646 available, that the type field will have other values that correspond to YUV
3649 Scatter-Gather Array
3650 ~~~~~~~~~~~~~~~~~~~~
3652 The scatter-gather array is a contiguously allocated block of memory that
3653 tells the card the source and destination of each data-block to transfer.
3654 Card "addresses" are derived from the offset supplied by Mailbox #10. Host
3655 addresses are the physical memory location of the target DMA buffer.
3657 Each S-G array element is a struct of three 32-bit words. The first word is
3658 the source address, the second is the destination address. Both take up the
3659 entire 32 bits. The lowest 18 bits of the third word is the transfer byte
3660 count. The high-bit of the third word is the "last" flag. The last-flag tells
3661 the card to raise the DMA_DONE interrupt. From hard personal experience, if
3662 you forget to set this bit, the card will still "work" but the stream will
3663 most likely get corrupted.
3665 The transfer count must be a multiple of 256. Therefore, the driver will need
3666 to track how much data in the target buffer is valid and deal with it
3671 - 32-bit Source Address
3672 - 32-bit Destination Address
3673 - 14-bit reserved (high bit is the last flag)
3679 Register 0x0004 holds the DMA Transfer Status:
3681 - bit 0: read completed
3682 - bit 1: write completed
3683 - bit 2: DMA read error
3684 - bit 3: DMA write error
3685 - bit 4: Scatter-Gather array error
3687 Non-compressed file format
3688 --------------------------
3690 The cx23416 can produce (and the cx23415 can also read) raw YUV output. The
3691 format of a YUV frame is specific to this chip and is called HM12. 'HM' stands
3692 for 'Hauppauge Macroblock', which is a misnomer as 'Conexant Macroblock' would
3695 The format is YUV 4:2:0 which uses 1 Y byte per pixel and 1 U and V byte per
3698 The data is encoded as two macroblock planes, the first containing the Y
3699 values, the second containing UV macroblocks.
3701 The Y plane is divided into blocks of 16x16 pixels from left to right
3702 and from top to bottom. Each block is transmitted in turn, line-by-line.
3704 So the first 16 bytes are the first line of the top-left block, the
3705 second 16 bytes are the second line of the top-left block, etc. After
3706 transmitting this block the first line of the block on the right to the
3707 first block is transmitted, etc.
3709 The UV plane is divided into blocks of 16x8 UV values going from left
3710 to right, top to bottom. Each block is transmitted in turn, line-by-line.
3712 So the first 16 bytes are the first line of the top-left block and
3713 contain 8 UV value pairs (16 bytes in total). The second 16 bytes are the
3714 second line of 8 UV pairs of the top-left block, etc. After transmitting
3715 this block the first line of the block on the right to the first block is
3718 The code below is given as an example on how to convert HM12 to separate
3719 Y, U and V planes. This code assumes frames of 720x576 (PAL) pixels.
3721 The width of a frame is always 720 pixels, regardless of the actual specified
3724 If the height is not a multiple of 32 lines, then the captured video is
3725 missing macroblocks at the end and is unusable. So the height must be a
3728 Raw format c example
3729 ~~~~~~~~~~~~~~~~~~~~
3737 static unsigned char frame[576*720*3/2];
3738 static unsigned char framey[576*720];
3739 static unsigned char frameu[576*720 / 4];
3740 static unsigned char framev[576*720 / 4];
3742 static void de_macro_y(unsigned char* dst, unsigned char *src, int dstride, int w, int h)
3744 unsigned int y, x, i;
3746 // descramble Y plane
3747 // dstride = 720 = w
3748 // The Y plane is divided into blocks of 16x16 pixels
3749 // Each block in transmitted in turn, line-by-line.
3750 for (y = 0; y < h; y += 16) {
3751 for (x = 0; x < w; x += 16) {
3752 for (i = 0; i < 16; i++) {
3753 memcpy(dst + x + (y + i) * dstride, src, 16);
3760 static void de_macro_uv(unsigned char *dstu, unsigned char *dstv, unsigned char *src, int dstride, int w, int h)
3762 unsigned int y, x, i;
3764 // descramble U/V plane
3765 // dstride = 720 / 2 = w
3766 // The U/V values are interlaced (UVUV...).
3767 // Again, the UV plane is divided into blocks of 16x16 UV values.
3768 // Each block in transmitted in turn, line-by-line.
3769 for (y = 0; y < h; y += 16) {
3770 for (x = 0; x < w; x += 8) {
3771 for (i = 0; i < 16; i++) {
3772 int idx = x + (y + i) * dstride;
3774 dstu[idx+0] = src[0]; dstv[idx+0] = src[1];
3775 dstu[idx+1] = src[2]; dstv[idx+1] = src[3];
3776 dstu[idx+2] = src[4]; dstv[idx+2] = src[5];
3777 dstu[idx+3] = src[6]; dstv[idx+3] = src[7];
3778 dstu[idx+4] = src[8]; dstv[idx+4] = src[9];
3779 dstu[idx+5] = src[10]; dstv[idx+5] = src[11];
3780 dstu[idx+6] = src[12]; dstv[idx+6] = src[13];
3781 dstu[idx+7] = src[14]; dstv[idx+7] = src[15];
3788 /*************************************************************************/
3789 int main(int argc, char **argv)
3794 if (argc == 1) fin = stdin;
3795 else fin = fopen(argv[1], "r");
3798 fprintf(stderr, "cannot open input\n");
3801 while (fread(frame, sizeof(frame), 1, fin) == 1) {
3802 de_macro_y(framey, frame, 720, 720, 576);
3803 de_macro_uv(frameu, framev, frame + 720 * 576, 720 / 2, 720 / 2, 576 / 2);
3804 fwrite(framey, sizeof(framey), 1, stdout);
3805 fwrite(framev, sizeof(framev), 1, stdout);
3806 fwrite(frameu, sizeof(frameu), 1, stdout);
3813 Format of embedded V4L2_MPEG_STREAM_VBI_FMT_IVTV VBI data
3814 ---------------------------------------------------------
3816 Author: Hans Verkuil <hverkuil@xs4all.nl>
3819 This section describes the V4L2_MPEG_STREAM_VBI_FMT_IVTV format of the VBI data
3820 embedded in an MPEG-2 program stream. This format is in part dictated by some
3821 hardware limitations of the ivtv driver (the driver for the Conexant cx23415/6
3822 chips), in particular a maximum size for the VBI data. Anything longer is cut
3823 off when the MPEG stream is played back through the cx23415.
3825 The advantage of this format is it is very compact and that all VBI data for
3826 all lines can be stored while still fitting within the maximum allowed size.
3828 The stream ID of the VBI data is 0xBD. The maximum size of the embedded data is
3829 4 + 43 * 36, which is 4 bytes for a header and 2 * 18 VBI lines with a 1 byte
3830 header and a 42 bytes payload each. Anything beyond this limit is cut off by
3831 the cx23415/6 firmware. Besides the data for the VBI lines we also need 36 bits
3832 for a bitmask determining which lines are captured and 4 bytes for a magic cookie,
3833 signifying that this data package contains V4L2_MPEG_STREAM_VBI_FMT_IVTV VBI data.
3834 If all lines are used, then there is no longer room for the bitmask. To solve this
3835 two different magic numbers were introduced:
3837 'itv0': After this magic number two unsigned longs follow. Bits 0-17 of the first
3838 unsigned long denote which lines of the first field are captured. Bits 18-31 of
3839 the first unsigned long and bits 0-3 of the second unsigned long are used for the
3842 'ITV0': This magic number assumes all VBI lines are captured, i.e. it implicitly
3843 implies that the bitmasks are 0xffffffff and 0xf.
3845 After these magic cookies (and the 8 byte bitmask in case of cookie 'itv0') the
3846 captured VBI lines start:
3848 For each line the least significant 4 bits of the first byte contain the data type.
3849 Possible values are shown in the table below. The payload is in the following 42
3852 Here is the list of possible data types:
3856 #define IVTV_SLICED_TYPE_TELETEXT 0x1 // Teletext (uses lines 6-22 for PAL)
3857 #define IVTV_SLICED_TYPE_CC 0x4 // Closed Captions (line 21 NTSC)
3858 #define IVTV_SLICED_TYPE_WSS 0x5 // Wide Screen Signal (line 23 PAL)
3859 #define IVTV_SLICED_TYPE_VPS 0x7 // Video Programming System (PAL) (line 16)
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