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2 DMAengine controller documentation
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8 Most of the Slave DMA controllers have the same general principles of
11 They have a given number of channels to use for the DMA transfers, and
12 a given number of requests lines.
14 Requests and channels are pretty much orthogonal. Channels can be used
15 to serve several to any requests. To simplify, channels are the
16 entities that will be doing the copy, and requests what endpoints are
19 The request lines actually correspond to physical lines going from the
20 DMA-eligible devices to the controller itself. Whenever the device
21 will want to start a transfer, it will assert a DMA request (DRQ) by
22 asserting that request line.
24 A very simple DMA controller would only take into account a single
25 parameter: the transfer size. At each clock cycle, it would transfer a
26 byte of data from one buffer to another, until the transfer size has
29 That wouldn't work well in the real world, since slave devices might
30 require a specific number of bits to be transferred in a single
31 cycle. For example, we may want to transfer as much data as the
32 physical bus allows to maximize performances when doing a simple
33 memory copy operation, but our audio device could have a narrower FIFO
34 that requires data to be written exactly 16 or 24 bits at a time. This
35 is why most if not all of the DMA controllers can adjust this, using a
36 parameter called the transfer width.
38 Moreover, some DMA controllers, whenever the RAM is used as a source
39 or destination, can group the reads or writes in memory into a buffer,
40 so instead of having a lot of small memory accesses, which is not
41 really efficient, you'll get several bigger transfers. This is done
42 using a parameter called the burst size, that defines how many single
43 reads/writes it's allowed to do without the controller splitting the
44 transfer into smaller sub-transfers.
46 Our theoretical DMA controller would then only be able to do transfers
47 that involve a single contiguous block of data. However, some of the
48 transfers we usually have are not, and want to copy data from
49 non-contiguous buffers to a contiguous buffer, which is called
52 DMAEngine, at least for mem2dev transfers, require support for
53 scatter-gather. So we're left with two cases here: either we have a
54 quite simple DMA controller that doesn't support it, and we'll have to
55 implement it in software, or we have a more advanced DMA controller,
56 that implements in hardware scatter-gather.
58 The latter are usually programmed using a collection of chunks to
59 transfer, and whenever the transfer is started, the controller will go
60 over that collection, doing whatever we programmed there.
62 This collection is usually either a table or a linked list. You will
63 then push either the address of the table and its number of elements,
64 or the first item of the list to one channel of the DMA controller,
65 and whenever a DRQ will be asserted, it will go through the collection
66 to know where to fetch the data from.
68 Either way, the format of this collection is completely dependent on
69 your hardware. Each DMA controller will require a different structure,
70 but all of them will require, for every chunk, at least the source and
71 destination addresses, whether it should increment these addresses or
72 not and the three parameters we saw earlier: the burst size, the
73 transfer width and the transfer size.
75 The one last thing is that usually, slave devices won't issue DRQ by
76 default, and you have to enable this in your slave device driver first
77 whenever you're willing to use DMA.
79 These were just the general memory-to-memory (also called mem2mem) or
80 memory-to-device (mem2dev) kind of transfers. Most devices often
81 support other kind of transfers or memory operations that dmaengine
82 support and will be detailed later in this document.
87 Historically, DMA controller drivers have been implemented using the
88 async TX API, to offload operations such as memory copy, XOR,
89 cryptography, etc., basically any memory to memory operation.
91 Over time, the need for memory to device transfers arose, and
92 dmaengine was extended. Nowadays, the async TX API is written as a
93 layer on top of dmaengine, and acts as a client. Still, dmaengine
94 accommodates that API in some cases, and made some design choices to
95 ensure that it stayed compatible.
97 For more information on the Async TX API, please look the relevant
98 documentation file in Documentation/crypto/async-tx-api.txt.
103 ``struct dma_device`` Initialization
104 ------------------------------------
106 Just like any other kernel framework, the whole DMAEngine registration
107 relies on the driver filling a structure and registering against the
108 framework. In our case, that structure is dma_device.
110 The first thing you need to do in your driver is to allocate this
111 structure. Any of the usual memory allocators will do, but you'll also
112 need to initialize a few fields in there:
114 - channels: should be initialized as a list using the
115 INIT_LIST_HEAD macro for example
118 should contain a bitmask of the supported source transfer width
121 should contain a bitmask of the supported destination transfer width
124 should contain a bitmask of the supported slave directions
125 (i.e. excluding mem2mem transfers)
127 - residue_granularity:
129 - Granularity of the transfer residue reported to dma_set_residue.
134 - Your device doesn't support any kind of residue
135 reporting. The framework will only know that a particular
136 transaction descriptor is done.
140 - Your device is able to report which chunks have been transferred
144 - Your device is able to report which burst have been transferred
146 - dev: should hold the pointer to the ``struct device`` associated
147 to your current driver instance.
149 Supported transaction types
150 ---------------------------
152 The next thing you need is to set which transaction types your device
153 (and driver) supports.
155 Our ``dma_device structure`` has a field called cap_mask that holds the
156 various types of transaction supported, and you need to modify this
157 mask using the dma_cap_set function, with various flags depending on
158 transaction types you support as an argument.
160 All those capabilities are defined in the ``dma_transaction_type enum``,
161 in ``include/linux/dmaengine.h``
163 Currently, the types available are:
167 - The device is able to do memory to memory copies
171 - The device is able to perform XOR operations on memory areas
173 - Used to accelerate XOR intensive tasks, such as RAID5
177 - The device is able to perform parity check using the XOR
178 algorithm against a memory buffer.
182 - The device is able to perform RAID6 P+Q computations, P being a
183 simple XOR, and Q being a Reed-Solomon algorithm.
187 - The device is able to perform parity check using RAID6 P+Q
188 algorithm against a memory buffer.
192 - The device is able to trigger a dummy transfer that will
193 generate periodic interrupts
195 - Used by the client drivers to register a callback that will be
196 called on a regular basis through the DMA controller interrupt
200 - The devices only supports slave transfers, and as such isn't
201 available for async transfers.
205 - Must not be set by the device, and will be set by the framework
208 - TODO: What is it about?
212 - The device can handle device to memory transfers, including
213 scatter-gather transfers.
215 - While in the mem2mem case we were having two distinct types to
216 deal with a single chunk to copy or a collection of them, here,
217 we just have a single transaction type that is supposed to
220 - If you want to transfer a single contiguous memory buffer,
221 simply build a scatter list with only one item.
225 - The device can handle cyclic transfers.
227 - A cyclic transfer is a transfer where the chunk collection will
228 loop over itself, with the last item pointing to the first.
230 - It's usually used for audio transfers, where you want to operate
231 on a single ring buffer that you will fill with your audio data.
235 - The device supports interleaved transfer.
237 - These transfers can transfer data from a non-contiguous buffer
238 to a non-contiguous buffer, opposed to DMA_SLAVE that can
239 transfer data from a non-contiguous data set to a continuous
242 - It's usually used for 2d content transfers, in which case you
243 want to transfer a portion of uncompressed data directly to the
246 These various types will also affect how the source and destination
247 addresses change over time.
249 Addresses pointing to RAM are typically incremented (or decremented)
250 after each transfer. In case of a ring buffer, they may loop
251 (DMA_CYCLIC). Addresses pointing to a device's register (e.g. a FIFO)
257 Our dma_device structure also requires a few function pointers in
258 order to implement the actual logic, now that we described what
259 operations we were able to perform.
261 The functions that we have to fill in there, and hence have to
262 implement, obviously depend on the transaction types you reported as
265 - ``device_alloc_chan_resources``
267 - ``device_free_chan_resources``
269 - These functions will be called whenever a driver will call
270 ``dma_request_channel`` or ``dma_release_channel`` for the first/last
271 time on the channel associated to that driver.
273 - They are in charge of allocating/freeing all the needed
274 resources in order for that channel to be useful for your driver.
276 - These functions can sleep.
278 - ``device_prep_dma_*``
280 - These functions are matching the capabilities you registered
283 - These functions all take the buffer or the scatterlist relevant
284 for the transfer being prepared, and should create a hardware
285 descriptor or a list of hardware descriptors from it
287 - These functions can be called from an interrupt context
289 - Any allocation you might do should be using the GFP_NOWAIT
290 flag, in order not to potentially sleep, but without depleting
291 the emergency pool either.
293 - Drivers should try to pre-allocate any memory they might need
294 during the transfer setup at probe time to avoid putting to
295 much pressure on the nowait allocator.
297 - It should return a unique instance of the
298 ``dma_async_tx_descriptor structure``, that further represents this
301 - This structure can be initialized using the function
302 ``dma_async_tx_descriptor_init``.
304 - You'll also need to set two fields in this structure:
307 TODO: Can it be modified by the driver itself, or
308 should it be always the flags passed in the arguments
310 - tx_submit: A pointer to a function you have to implement,
311 that is supposed to push the current transaction descriptor to a
312 pending queue, waiting for issue_pending to be called.
314 - In this structure the function pointer callback_result can be
315 initialized in order for the submitter to be notified that a
316 transaction has completed. In the earlier code the function pointer
317 callback has been used. However it does not provide any status to the
318 transaction and will be deprecated. The result structure defined as
319 ``dmaengine_result`` that is passed in to callback_result
322 - result: This provides the transfer result defined by
323 ``dmaengine_tx_result``. Either success or some error condition.
325 - residue: Provides the residue bytes of the transfer for those that
328 - ``device_issue_pending``
330 - Takes the first transaction descriptor in the pending queue,
331 and starts the transfer. Whenever that transfer is done, it
332 should move to the next transaction in the list.
334 - This function can be called in an interrupt context
336 - ``device_tx_status``
338 - Should report the bytes left to go over on the given channel
340 - Should only care about the transaction descriptor passed as
341 argument, not the currently active one on a given channel
343 - The tx_state argument might be NULL
345 - Should use dma_set_residue to report it
347 - In the case of a cyclic transfer, it should only take into
348 account the current period.
350 - This function can be called in an interrupt context.
354 - Reconfigures the channel with the configuration given as argument
356 - This command should NOT perform synchronously, or on any
357 currently queued transfers, but only on subsequent ones
359 - In this case, the function will receive a ``dma_slave_config``
360 structure pointer as an argument, that will detail which
361 configuration to use.
363 - Even though that structure contains a direction field, this
364 field is deprecated in favor of the direction argument given to
367 - This call is mandatory for slave operations only. This should NOT be
368 set or expected to be set for memcpy operations.
369 If a driver support both, it should use this call for slave
370 operations only and not for memcpy ones.
374 - Pauses a transfer on the channel
376 - This command should operate synchronously on the channel,
377 pausing right away the work of the given channel
381 - Resumes a transfer on the channel
383 - This command should operate synchronously on the channel,
384 resuming right away the work of the given channel
386 - device_terminate_all
388 - Aborts all the pending and ongoing transfers on the channel
390 - For aborted transfers the complete callback should not be called
392 - Can be called from atomic context or from within a complete
393 callback of a descriptor. Must not sleep. Drivers must be able
394 to handle this correctly.
396 - Termination may be asynchronous. The driver does not have to
397 wait until the currently active transfer has completely stopped.
398 See device_synchronize.
402 - Must synchronize the termination of a channel to the current
405 - Must make sure that memory for previously submitted
406 descriptors is no longer accessed by the DMA controller.
408 - Must make sure that all complete callbacks for previously
409 submitted descriptors have finished running and none are
418 (stuff that should be documented, but don't really know
421 ``dma_run_dependencies``
423 - Should be called at the end of an async TX transfer, and can be
424 ignored in the slave transfers case.
426 - Makes sure that dependent operations are run before marking it
431 - it's a DMA transaction ID that will increment over time.
433 - Not really relevant any more since the introduction of ``virt-dma``
434 that abstracts it away.
438 - If clear, the descriptor cannot be reused by provider until the
439 client acknowledges receipt, i.e. has has a chance to establish any
442 - This can be acked by invoking async_tx_ack()
444 - If set, does not mean descriptor can be reused
448 - If set, the descriptor can be reused after being completed. It should
449 not be freed by provider if this flag is set.
451 - The descriptor should be prepared for reuse by invoking
452 ``dmaengine_desc_set_reuse()`` which will set DMA_CTRL_REUSE.
454 - ``dmaengine_desc_set_reuse()`` will succeed only when channel support
455 reusable descriptor as exhibited by capabilities
457 - As a consequence, if a device driver wants to skip the
458 ``dma_map_sg()`` and ``dma_unmap_sg()`` in between 2 transfers,
459 because the DMA'd data wasn't used, it can resubmit the transfer right after
462 - Descriptor can be freed in few ways
464 - Clearing DMA_CTRL_REUSE by invoking
465 ``dmaengine_desc_clear_reuse()`` and submitting for last txn
467 - Explicitly invoking ``dmaengine_desc_free()``, this can succeed only
468 when DMA_CTRL_REUSE is already set
470 - Terminating the channel
474 - If set, the client driver tells DMA controller that passed data in DMA
477 - Interpretation of command data is DMA controller specific. It can be
478 used for issuing commands to other peripherals/register reads/register
479 writes for which the descriptor should be in different format from
480 normal data descriptors.
485 Most of the DMAEngine drivers you'll see are based on a similar design
486 that handles the end of transfer interrupts in the handler, but defer
487 most work to a tasklet, including the start of a new transfer whenever
488 the previous transfer ended.
490 This is a rather inefficient design though, because the inter-transfer
491 latency will be not only the interrupt latency, but also the
492 scheduling latency of the tasklet, which will leave the channel idle
493 in between, which will slow down the global transfer rate.
495 You should avoid this kind of practice, and instead of electing a new
496 transfer in your tasklet, move that part to the interrupt handler in
497 order to have a shorter idle window (that we can't really avoid
503 - Burst: A number of consecutive read or write operations that
504 can be queued to buffers before being flushed to memory.
506 - Chunk: A contiguous collection of bursts
508 - Transfer: A collection of chunks (be it contiguous or not)