1 * Universal Flash Storage (UFS) Host Controller
3 UFSHC nodes are defined to describe on-chip UFS host controllers.
4 Each UFS controller instance should have its own node.
7 - compatible : must contain "jedec,ufs-1.1" or "jedec,ufs-2.0", may
8 also list one or more of the following:
12 - interrupts : <interrupt mapping for UFS host controller IRQ>
13 - reg : <registers mapping>
16 - phys : phandle to UFS PHY node
17 - phy-names : the string "ufsphy" when is found in a node, along
18 with "phys" attribute, provides phandle to UFS PHY node
19 - vdd-hba-supply : phandle to UFS host controller supply regulator node
20 - vcc-supply : phandle to VCC supply regulator node
21 - vccq-supply : phandle to VCCQ supply regulator node
22 - vccq2-supply : phandle to VCCQ2 supply regulator node
23 - vcc-supply-1p8 : For embedded UFS devices, valid VCC range is 1.7-1.95V
24 or 2.7-3.6V. This boolean property when set, specifies
25 to use low voltage range of 1.7-1.95V. Note for external
26 UFS cards this property is invalid and valid VCC range is
28 - vcc-max-microamp : specifies max. load that can be drawn from vcc supply
29 - vccq-max-microamp : specifies max. load that can be drawn from vccq supply
30 - vccq2-max-microamp : specifies max. load that can be drawn from vccq2 supply
31 - <name>-fixed-regulator : boolean property specifying that <name>-supply is a fixed regulator
33 - clocks : List of phandle and clock specifier pairs
34 - clock-names : List of clock input name strings sorted in the same
35 order as the clocks property.
36 "ref_clk" indicates reference clock frequency.
37 UFS host supplies reference clock to UFS device and UFS device
38 specification allows host to provide one of the 4 frequencies (19.2 MHz,
39 26 MHz, 38.4 MHz, 52MHz) for reference clock. This "ref_clk" entry is
40 parsed and used to update the reference clock setting in device.
41 Defaults to 26 MHz(as per specification) if not specified by host.
42 - freq-table-hz : Array of <min max> operating frequencies stored in the same
43 order as the clocks property. If this property is not
44 defined or a value in the array is "0" then it is assumed
45 that the frequency is set by the parent clock or a
46 fixed rate clock source.
47 -lanes-per-direction : number of lanes available per direction - either 1 or 2.
48 Note that it is assume same number of lanes is used both
49 directions at once. If not specified, default is 2 lanes per direction.
50 - resets : reset node register
51 - reset-names : describe reset node register, the "rst" corresponds to reset the whole UFS IP.
53 Note: If above properties are not defined it can be assumed that the supply
54 regulators or clocks are always on.
58 compatible = "jedec,ufs-1.1";
59 reg = <0xfc598000 0x800>;
60 interrupts = <0 28 0>;
62 vdd-hba-supply = <&xxx_reg0>;
63 vdd-hba-fixed-regulator;
64 vcc-supply = <&xxx_reg1>;
66 vccq-supply = <&xxx_reg2>;
67 vccq2-supply = <&xxx_reg3>;
68 vcc-max-microamp = 500000;
69 vccq-max-microamp = 200000;
70 vccq2-max-microamp = 200000;
72 clocks = <&core 0>, <&ref 0>, <&phy 0>, <&iface 0>;
73 clock-names = "core_clk", "ref_clk", "phy_clk", "iface_clk";
74 freq-table-hz = <100000000 200000000>, <0 0>, <0 0>, <0 0>;
75 resets = <&reset 0 1>;