1 * STMicroelectronics Quad Serial Peripheral Interface(QSPI)
4 - compatible: should be "st,stm32f469-qspi"
5 - reg: the first contains the register location and length.
6 the second contains the memory mapping address and length
7 - reg-names: should contain the reg names "qspi" "qspi_mm"
8 - interrupts: should contain the interrupt for the device
9 - clocks: the phandle of the clock needed by the QSPI controller
10 - A pinctrl must be defined to set pins in mode of operation for QSPI transfer
13 - resets: must contain the phandle to the reset controller.
15 A spi flash (NOR/NAND) must be a child of spi node and could have some
16 properties. Also see jedec,spi-nor.txt.
19 - reg: chip-Select number (QSPI controller may connect 2 flashes)
20 - spi-max-frequency: max frequency of spi bus
23 - spi-rx-bus-width: see ./spi-bus.txt for the description
24 - dmas: DMA specifiers for tx and rx dma. See the DMA client binding,
25 Documentation/devicetree/bindings/dma/dma.txt.
26 - dma-names: DMA request names should include "tx" and "rx" if present.
31 compatible = "st,stm32f469-qspi";
32 reg = <0xa0001000 0x1000>, <0x90000000 0x10000000>;
33 reg-names = "qspi", "qspi_mm";
35 resets = <&rcc STM32F4_AHB3_RESET(QSPI)>;
36 clocks = <&rcc 0 STM32F4_AHB3_CLOCK(QSPI)>;
37 pinctrl-names = "default";
38 pinctrl-0 = <&pinctrl_qspi0>;
41 compatible = "jedec,spi-nor";
43 spi-rx-bus-width = <4>;
44 spi-max-frequency = <108000000>;