Documentation/devicetree/bindings/spi/qcom,spi-qup.txt

   1 Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI)
   2
   3 The QUP core is an AHB slave that provides a common data path (an output FIFO
   4 and an input FIFO) for serial peripheral interface (SPI) mini-core.
   5
   6 SPI in master mode supports up to 50MHz, up to four chip selects, programmable
   7 data path from 4 bits to 32 bits and numerous protocol variants.
   8
   9 Required properties:
  10 - compatible:     Should contain:
  11                   "qcom,spi-qup-v1.1.1" for 8660, 8960 and 8064.
  12                   "qcom,spi-qup-v2.1.1" for 8974 and later
  13                   "qcom,spi-qup-v2.2.1" for 8974 v2 and later.
  14
  15 - reg:            Should contain base register location and length
  16 - interrupts:     Interrupt number used by this controller
  17
  18 - clocks:         Should contain the core clock and the AHB clock.
  19 - clock-names:    Should be "core" for the core clock and "iface" for the
  20                   AHB clock.
  21
  22 - #address-cells: Number of cells required to define a chip select
  23                   address on the SPI bus. Should be set to 1.
  24 - #size-cells:    Should be zero.
  25
  26 Optional properties:
  27 - spi-max-frequency: Specifies maximum SPI clock frequency,
  28                      Units - Hz. Definition as per
  29                      Documentation/devicetree/bindings/spi/spi-bus.txt
  30 - num-cs:       total number of chipselects
  31 - cs-gpios:     should specify GPIOs used for chipselects.
  32                 The gpios will be referred to as reg = <index> in the SPI child
  33                 nodes.  If unspecified, a single SPI device without a chip
  34                 select can be used.
  35
  36
  37 SPI slave nodes must be children of the SPI master node and can contain
  38 properties described in Documentation/devicetree/bindings/spi/spi-bus.txt
  39
  40 Example:
  41
  42         spi_8: spi@f9964000 { /* BLSP2 QUP2 */
  43
  44                 compatible = "qcom,spi-qup-v2";
  45                 #address-cells = <1>;
  46                 #size-cells = <0>;
  47                 reg = <0xf9964000 0x1000>;
  48                 interrupts = <0 102 0>;
  49                 spi-max-frequency = <19200000>;
  50
  51                 clocks = <&gcc GCC_BLSP2_QUP2_SPI_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
  52                 clock-names = "core", "iface";
  53
  54                 pinctrl-names = "default";
  55                 pinctrl-0 = <&spi8_default>;
  56
  57                 device@0 {
  58                         compatible = "arm,pl022-dummy";
  59                         #address-cells = <1>;
  60                         #size-cells = <1>;
  61                         reg = <0>; /* Chip select 0 */
  62                         spi-max-frequency = <19200000>;
  63                         spi-cpol;
  64                 };
  65
  66                 device@1 {
  67                         compatible = "arm,pl022-dummy";
  68                         #address-cells = <1>;
  69                         #size-cells = <1>;
  70                         reg = <1>; /* Chip select 1 */
  71                         spi-max-frequency = <9600000>;
  72                         spi-cpha;
  73                 };
  74
  75                 device@2 {
  76                         compatible = "arm,pl022-dummy";
  77                         #address-cells = <1>;
  78                         #size-cells = <1>;
  79                         reg = <2>; /* Chip select 2 */
  80                         spi-max-frequency = <19200000>;
  81                         spi-cpol;
  82                         spi-cpha;
  83                 };
  84
  85                 device@3 {
  86                         compatible = "arm,pl022-dummy";
  87                         #address-cells = <1>;
  88                         #size-cells = <1>;
  89                         reg = <3>; /* Chip select 3 */
  90                         spi-max-frequency = <19200000>;
  91                         spi-cpol;
  92                         spi-cpha;
  93                         spi-cs-high;
  94                 };
  95         };