1 SiFive asynchronous serial interface (UART)
5 - compatible: should be something similar to
6 "sifive,<chip>-uart" for the UART as integrated
7 on a particular chip, and "sifive,uart<version>" for the
8 general UART IP block programming model. Supported
9 compatible strings as of the date of this writing are:
10 "sifive,fu540-c000-uart" for the SiFive UART v0 as
11 integrated onto the SiFive FU540 chip, or "sifive,uart0"
12 for the SiFive UART v0 IP block with no chip integration
14 - reg: address and length of the register space
15 - interrupts: Should contain the UART interrupt identifier
16 - clocks: Should contain a clock identifier for the UART's parent clock
19 UART HDL that corresponds to the IP block version numbers can be found
22 https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/uart
27 uart0: serial@10010000 {
28 compatible = "sifive,fu540-c000-uart", "sifive,uart0";
29 interrupt-parent = <&plic0>;
31 reg = <0x0 0x10010000 0x0 0x1000>;
32 clocks = <&prci PRCI_CLK_TLCLK>;