1 * Freescale low power universal asynchronous receiver/transmitter (lpuart)
5 - "fsl,vf610-lpuart" for lpuart compatible with the one integrated
6 on Vybrid vf610 SoC with 8-bit register organization
7 - "fsl,ls1021a-lpuart" for lpuart compatible with the one integrated
8 on LS1021A SoC with 32-bit big-endian register organization
9 - "fsl,imx7ulp-lpuart" for lpuart compatible with the one integrated
10 on i.MX7ULP SoC with 32-bit little-endian register organization
11 - "fsl,imx8qxp-lpuart" for lpuart compatible with the one integrated
12 on i.MX8QXP SoC with 32-bit little-endian register organization
13 - reg : Address and length of the register set for the device
14 - interrupts : Should contain uart interrupt
15 - clocks : phandle + clock specifier pairs, one for each entry in clock-names
16 - clock-names : For vf610/ls1021a/imx7ulp, "ipg" clock is for uart bus/baud
17 clock. For imx8qxp lpuart, "ipg" clock is bus clock that is used to access
18 lpuart controller registers, it also requires "baud" clock for module to
19 receive/transmit data.
22 - dmas: A list of two dma specifiers, one for each entry in dma-names.
23 - dma-names: should contain "tx" and "rx".
24 - rs485-rts-delay, rs485-rts-active-low, rs485-rx-during-tx,
25 linux,rs485-enabled-at-boot-time: see rs485.txt
27 Note: Optional properties for DMA support. Write them both or both not.
31 uart0: serial@40027000 {
32 compatible = "fsl,vf610-lpuart";
33 reg = <0x40027000 0x1000>;
34 interrupts = <0 61 0x00>;
35 clocks = <&clks VF610_CLK_UART0>;
39 dma-names = "rx","tx";