Documentation/devicetree/bindings/riscv/cpus.yaml

   1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/riscv/cpus.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: RISC-V bindings for 'cpus' DT nodes
   8
   9 maintainers:
  10   - Paul Walmsley <paul.walmsley@sifive.com>
  11   - Palmer Dabbelt <palmer@sifive.com>
  12
  13 allOf:
  14   - $ref: /schemas/cpus.yaml#
  15
  16 properties:
  17   $nodename:
  18     const: cpus
  19     description: Container of cpu nodes
  20
  21   '#address-cells':
  22     const: 1
  23     description: |
  24       A single unsigned 32-bit integer uniquely identifies each RISC-V
  25       hart in a system.  (See the "reg" node under the "cpu" node,
  26       below).
  27
  28   '#size-cells':
  29     const: 0
  30
  31 patternProperties:
  32   '^cpu@[0-9a-f]+$':
  33     properties:
  34       compatible:
  35         type: array
  36         items:
  37           - enum:
  38               - sifive,rocket0
  39               - sifive,e5
  40               - sifive,e51
  41               - sifive,u54-mc
  42               - sifive,u54
  43               - sifive,u5
  44           - const: riscv
  45         description:
  46           Identifies that the hart uses the RISC-V instruction set
  47           and identifies the type of the hart.
  48
  49       mmu-type:
  50         allOf:
  51           - $ref: "/schemas/types.yaml#/definitions/string"
  52           - enum:
  53               - riscv,sv32
  54               - riscv,sv39
  55               - riscv,sv48
  56         description:
  57           Identifies the MMU address translation mode used on this
  58           hart.  These values originate from the RISC-V Privileged
  59           Specification document, available from
  60           https://riscv.org/specifications/
  61
  62       riscv,isa:
  63         allOf:
  64           - $ref: "/schemas/types.yaml#/definitions/string"
  65           - enum:
  66               - rv64imac
  67               - rv64imafdc
  68         description:
  69           Identifies the specific RISC-V instruction set architecture
  70           supported by the hart.  These are documented in the RISC-V
  71           User-Level ISA document, available from
  72           https://riscv.org/specifications/
  73
  74       timebase-frequency:
  75         type: integer
  76         minimum: 1
  77         description:
  78           Specifies the clock frequency of the system timer in Hz.
  79           This value is common to all harts on a single system image.
  80
  81       interrupt-controller:
  82         type: object
  83         description: Describes the CPU's local interrupt controller
  84
  85         properties:
  86           '#interrupt-cells':
  87             const: 1
  88
  89           compatible:
  90             const: riscv,cpu-intc
  91
  92           interrupt-controller: true
  93
  94         required:
  95           - '#interrupt-cells'
  96           - compatible
  97           - interrupt-controller
  98
  99     required:
 100       - riscv,isa
 101       - timebase-frequency
 102       - interrupt-controller
 103
 104 examples:
 105   - |
 106     // Example 1: SiFive Freedom U540G Development Kit
 107     cpus {
 108         #address-cells = <1>;
 109         #size-cells = <0>;
 110         timebase-frequency = <1000000>;
 111         cpu@0 {
 112                 clock-frequency = <0>;
 113                 compatible = "sifive,rocket0", "riscv";
 114                 device_type = "cpu";
 115                 i-cache-block-size = <64>;
 116                 i-cache-sets = <128>;
 117                 i-cache-size = <16384>;
 118                 reg = <0>;
 119                 riscv,isa = "rv64imac";
 120                 cpu_intc0: interrupt-controller {
 121                         #interrupt-cells = <1>;
 122                         compatible = "riscv,cpu-intc";
 123                         interrupt-controller;
 124                 };
 125         };
 126         cpu@1 {
 127                 clock-frequency = <0>;
 128                 compatible = "sifive,rocket0", "riscv";
 129                 d-cache-block-size = <64>;
 130                 d-cache-sets = <64>;
 131                 d-cache-size = <32768>;
 132                 d-tlb-sets = <1>;
 133                 d-tlb-size = <32>;
 134                 device_type = "cpu";
 135                 i-cache-block-size = <64>;
 136                 i-cache-sets = <64>;
 137                 i-cache-size = <32768>;
 138                 i-tlb-sets = <1>;
 139                 i-tlb-size = <32>;
 140                 mmu-type = "riscv,sv39";
 141                 reg = <1>;
 142                 riscv,isa = "rv64imafdc";
 143                 tlb-split;
 144                 cpu_intc1: interrupt-controller {
 145                         #interrupt-cells = <1>;
 146                         compatible = "riscv,cpu-intc";
 147                         interrupt-controller;
 148                 };
 149         };
 150     };
 151
 152   - |
 153     // Example 2: Spike ISA Simulator with 1 Hart
 154     cpus {
 155         #address-cells = <1>;
 156         #size-cells = <0>;
 157         cpu@0 {
 158                 device_type = "cpu";
 159                 reg = <0>;
 160                 compatible = "riscv";
 161                 riscv,isa = "rv64imafdc";
 162                 mmu-type = "riscv,sv48";
 163                 interrupt-controller {
 164                         #interrupt-cells = <1>;
 165                         interrupt-controller;
 166                         compatible = "riscv,cpu-intc";
 167                 };
 168         };
 169     };
 170 ...