1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/reset/intel,rcu-gw.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: System Reset Controller on Intel Gateway SoCs
10 - Dilip Kota <eswara.kota@linux.intel.com>
19 description: Reset controller registers.
23 description: Global reset register offset and bit offset.
25 - $ref: /schemas/types.yaml#/definitions/uint32-array
32 First cell is reset request register offset.
33 Second cell is bit offset in reset request register.
34 Third cell is bit offset in reset status register.
35 For LGM SoC, reset cell count is 2 as bit offset in
36 reset request and reset status registers is same. Whereas
37 3 for legacy SoCs as bit offset differs.
45 additionalProperties: false
49 rcu0: reset-controller@e0000000 {
50 compatible = "intel,rcu-lgm";
51 reg = <0xe0000000 0x20000>;
52 intel,global-reset = <0x10 30>;
58 compatible = "intel,lgm-pwm";
59 reg = <0xe0d00000 0x30>;
62 resets = <&rcu0 0x30 21>;