Documentation/devicetree/bindings/remoteproc/qcom,adsp-pil.txt

   1 Qualcomm Technology Inc. ADSP Peripheral Image Loader
   2
   3 This document defines the binding for a component that loads and boots firmware
   4 on the Qualcomm Technology Inc. ADSP Hexagon core.
   5
   6 - compatible:
   7         Usage: required
   8         Value type: <string>
   9         Definition: must be one of:
  10                     "qcom,sdm845-adsp-pil"
  11
  12 - reg:
  13         Usage: required
  14         Value type: <prop-encoded-array>
  15         Definition: must specify the base address and size of the qdsp6ss register
  16
  17 - interrupts-extended:
  18         Usage: required
  19         Value type: <prop-encoded-array>
  20         Definition: must list the watchdog, fatal IRQs ready, handover and
  21                     stop-ack IRQs
  22
  23 - interrupt-names:
  24         Usage: required
  25         Value type: <stringlist>
  26         Definition: must be "wdog", "fatal", "ready", "handover", "stop-ack"
  27
  28 - clocks:
  29         Usage: required
  30         Value type: <prop-encoded-array>
  31         Definition:  List of 8 phandle and clock specifier pairs for the adsp.
  32
  33 - clock-names:
  34         Usage: required
  35         Value type: <stringlist>
  36         Definition: List of clock input name strings sorted in the same
  37                     order as the clocks property. Definition must have
  38                     "xo", "sway_cbcr", "lpass_aon", "lpass_ahbs_aon_cbcr",
  39                     "lpass_ahbm_aon_cbcr", "qdsp6ss_xo", "qdsp6ss_sleep"
  40                     and "qdsp6ss_core".
  41
  42 - power-domains:
  43         Usage: required
  44         Value type: <phandle>
  45         Definition: reference to cx power domain node.
  46
  47 - resets:
  48         Usage: required
  49         Value type: <phandle>
  50         Definition: reference to the list of 2 reset-controller for the adsp.
  51
  52 - reset-names:
  53         Usage: required
  54         Value type: <stringlist>
  55         Definition: must be "pdc_sync" and "cc_lpass"
  56
  57 - qcom,halt-regs:
  58         Usage: required
  59         Value type: <prop-encoded-array>
  60         Definition: a phandle reference to a syscon representing TCSR followed
  61                         by the offset within syscon for lpass halt register.
  62
  63 - memory-region:
  64         Usage: required
  65         Value type: <phandle>
  66         Definition: reference to the reserved-memory for the ADSP
  67
  68 - qcom,smem-states:
  69         Usage: required
  70         Value type: <phandle>
  71         Definition: reference to the smem state for requesting the ADSP to
  72                     shut down
  73
  74 - qcom,smem-state-names:
  75         Usage: required
  76         Value type: <stringlist>
  77         Definition: must be "stop"
  78
  79
  80 = SUBNODES
  81 The adsp node may have an subnode named "glink-edge" that describes the
  82 communication edge, channels and devices related to the ADSP.
  83 See ../soc/qcom/qcom,glink.txt for details on how to describe these.
  84
  85 = EXAMPLE
  86 The following example describes the resources needed to boot control the
  87 ADSP, as it is found on SDM845 boards.
  88
  89         remoteproc@17300000 {
  90                 compatible = "qcom,sdm845-adsp-pil";
  91                 reg = <0x17300000 0x40c>;
  92
  93                 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
  94                         <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
  95                         <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
  96                         <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
  97                         <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
  98                 interrupt-names = "wdog", "fatal", "ready",
  99                         "handover", "stop-ack";
 100
 101                 clocks = <&rpmhcc RPMH_CXO_CLK>,
 102                         <&gcc GCC_LPASS_SWAY_CLK>,
 103                         <&lpasscc LPASS_AUDIO_WRAPPER_AON_CLK>,
 104                         <&lpasscc LPASS_Q6SS_AHBS_AON_CLK>,
 105                         <&lpasscc LPASS_Q6SS_AHBM_AON_CLK>,
 106                         <&lpasscc LPASS_QDSP6SS_XO_CLK>,
 107                         <&lpasscc LPASS_QDSP6SS_SLEEP_CLK>,
 108                         <&lpasscc LPASS_QDSP6SS_CORE_CLK>;
 109                 clock-names = "xo", "sway_cbcr", "lpass_aon",
 110                         "lpass_ahbs_aon_cbcr",
 111                         "lpass_ahbm_aon_cbcr", "qdsp6ss_xo",
 112                         "qdsp6ss_sleep", "qdsp6ss_core";
 113
 114                 power-domains = <&rpmhpd SDM845_CX>;
 115
 116                 resets = <&pdc_reset PDC_AUDIO_SYNC_RESET>,
 117                          <&aoss_reset AOSS_CC_LPASS_RESTART>;
 118                 reset-names = "pdc_sync", "cc_lpass";
 119
 120                 qcom,halt-regs = <&tcsr_mutex_regs 0x22000>;
 121
 122                 memory-region = <&pil_adsp_mem>;
 123
 124                 qcom,smem-states = <&adsp_smp2p_out 0>;
 125                 qcom,smem-state-names = "stop";
 126         };