Documentation/devicetree/bindings/regulator/uniphier-regulator.txt

   1 Socionext UniPhier Regulator Controller
   2
   3 This describes the devicetree bindings for regulator controller implemented
   4 on Socionext UniPhier SoCs.
   5
   6 USB3 Controller
   7 ---------------
   8
   9 This regulator controls VBUS and belongs to USB3 glue layer. Before using
  10 the regulator, it is necessary to control the clocks and resets to enable
  11 this layer. These clocks and resets should be described in each property.
  12
  13 Required properties:
  14 - compatible: Should be
  15     "socionext,uniphier-pro4-usb3-regulator" - for Pro4 SoC
  16     "socionext,uniphier-pxs2-usb3-regulator" - for PXs2 SoC
  17     "socionext,uniphier-ld20-usb3-regulator" - for LD20 SoC
  18     "socionext,uniphier-pxs3-usb3-regulator" - for PXs3 SoC
  19 - reg: Specifies offset and length of the register set for the device.
  20 - clocks: A list of phandles to the clock gate for USB3 glue layer.
  21         According to the clock-names, appropriate clocks are required.
  22 - clock-names: Should contain
  23     "gio", "link" - for Pro4 SoC
  24     "link"        - for others
  25 - resets: A list of phandles to the reset control for USB3 glue layer.
  26         According to the reset-names, appropriate resets are required.
  27 - reset-names: Should contain
  28     "gio", "link" - for Pro4 SoC
  29     "link"        - for others
  30
  31 See Documentation/devicetree/bindings/regulator/regulator.txt
  32 for more details about the regulator properties.
  33
  34 Example:
  35
  36         usb-glue@65b00000 {
  37                 compatible = "socionext,uniphier-ld20-dwc3-glue",
  38                              "simple-mfd";
  39                 #address-cells = <1>;
  40                 #size-cells = <1>;
  41                 ranges = <0 0x65b00000 0x400>;
  42
  43                 usb_vbus0: regulators@100 {
  44                         compatible = "socionext,uniphier-ld20-usb3-regulator";
  45                         reg = <0x100 0x10>;
  46                         clock-names = "link";
  47                         clocks = <&sys_clk 14>;
  48                         reset-names = "link";
  49                         resets = <&sys_rst 14>;
  50                 };
  51
  52                 phy {
  53                         ...
  54                         phy-supply = <&usb_vbus0>;
  55                 };
  56                 ...
  57         };