Documentation/devicetree/bindings/power/fsl,imx-gpc.txt

   1 Freescale i.MX General Power Controller
   2 =======================================
   3
   4 The i.MX6 General Power Control (GPC) block contains DVFS load tracking
   5 counters and Power Gating Control (PGC).
   6
   7 Required properties:
   8 - compatible: Should be one of the following:
   9   - fsl,imx6q-gpc
  10   - fsl,imx6qp-gpc
  11   - fsl,imx6sl-gpc
  12 - reg: should be register base and length as documented in the
  13   datasheet
  14 - interrupts: Should contain one interrupt specifier for the GPC interrupt
  15 - clocks: Must contain an entry for each entry in clock-names.
  16   See Documentation/devicetree/bindings/clocks/clock-bindings.txt for details.
  17 - clock-names: Must include the following entries:
  18   - ipg
  19
  20 The power domains are generic power domain providers as documented in
  21 Documentation/devicetree/bindings/power/power_domain.txt. They are described as
  22 subnodes of the power gating controller 'pgc' node of the GPC and should
  23 contain the following:
  24
  25 Required properties:
  26 - reg: Must contain the DOMAIN_INDEX of this power domain
  27   The following DOMAIN_INDEX values are valid for i.MX6Q:
  28   ARM_DOMAIN     0
  29   PU_DOMAIN      1
  30   The following additional DOMAIN_INDEX value is valid for i.MX6SL:
  31   DISPLAY_DOMAIN 2
  32
  33 - #power-domain-cells: Should be 0
  34
  35 Optional properties:
  36 - clocks: a number of phandles to clocks that need to be enabled during domain
  37   power-up sequencing to ensure reset propagation into devices located inside
  38   this power domain
  39 - power-supply: a phandle to the regulator powering this domain
  40
  41 Example:
  42
  43         gpc: gpc@20dc000 {
  44                 compatible = "fsl,imx6q-gpc";
  45                 reg = <0x020dc000 0x4000>;
  46                 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
  47                              <0 90 IRQ_TYPE_LEVEL_HIGH>;
  48                 clocks = <&clks IMX6QDL_CLK_IPG>;
  49                 clock-names = "ipg";
  50
  51                 pgc {
  52                         #address-cells = <1>;
  53                         #size-cells = <0>;
  54
  55                         power-domain@0 {
  56                                 reg = <0>;
  57                                 #power-domain-cells = <0>;
  58                         };
  59
  60                         pd_pu: power-domain@1 {
  61                                 reg = <1>;
  62                                 #power-domain-cells = <0>;
  63                                 power-supply = <&reg_pu>;
  64                                 clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
  65                                          <&clks IMX6QDL_CLK_GPU3D_SHADER>,
  66                                          <&clks IMX6QDL_CLK_GPU2D_CORE>,
  67                                          <&clks IMX6QDL_CLK_GPU2D_AXI>,
  68                                          <&clks IMX6QDL_CLK_OPENVG_AXI>,
  69                                          <&clks IMX6QDL_CLK_VPU_AXI>;
  70                         };
  71                 };
  72         };
  73
  74
  75 Specifying power domain for IP modules
  76 ======================================
  77
  78 IP cores belonging to a power domain should contain a 'power-domains' property
  79 that is a phandle pointing to the power domain the device belongs to.
  80
  81 Example of a device that is part of the PU power domain:
  82
  83         vpu: vpu@2040000 {
  84                 reg = <0x02040000 0x3c000>;
  85                 /* ... */
  86                 power-domains = <&pd_pu>;
  87                 /* ... */
  88         };