1 * STM32 GPIO and Pin Mux/Config controller
3 STMicroelectronics's STM32 MCUs intregrate a GPIO and Pin mux/config hardware
4 controller. It controls the input/output settings on the available pins and
5 also provides ability to multiplex and configure the output of various on-chip
6 controllers onto these pads.
10 - compatible: value should be one of the following:
11 "st,stm32f429-pinctrl"
12 "st,stm32f469-pinctrl"
13 "st,stm32f746-pinctrl"
14 "st,stm32f769-pinctrl"
15 "st,stm32h743-pinctrl"
16 "st,stm32mp157-pinctrl"
17 "st,stm32mp157-z-pinctrl"
18 - #address-cells: The value of this property must be 1
19 - #size-cells : The value of this property must be 1
20 - ranges : defines mapping between pin controller node (parent) to
21 gpio-bank node (children).
22 - pins-are-numbered: Specify the subnodes are using numbered pinmux to
25 GPIO controller/bank node:
27 - gpio-controller : Indicates this device is a GPIO controller
28 - #gpio-cells : Should be two.
29 The first cell is the pin number
30 The second one is the polarity:
33 - reg : The gpio address range, relative to the pinctrl range
34 - clocks : clock that drives this bank
35 - st,bank-name : Should be a name string for this bank as specified in
39 - reset: : Reference to the reset controller
40 - interrupt-parent: phandle of the interrupt parent to which the external
41 GPIO interrupts are forwarded to.
42 - st,syscfg: Should be phandle/offset pair. The phandle to the syscon node
43 which includes IRQ mux selection register, and the offset of the IRQ mux
45 - gpio-ranges: Define a dedicated mapping between a pin-controller and
46 a gpio controller. Format is <&phandle a b c> with:
47 -(phandle): phandle of pin-controller.
48 -(a): gpio base offset in range.
49 -(b): pin base offset in range.
50 -(c): gpio count in range
51 This entry has to be used either if there are holes inside a bank:
52 GPIOB0/B1/B2/B14/B15 (see example 2)
53 or if banks are not contiguous:
55 NOTE: If "gpio-ranges" is used for a gpio controller, all gpio-controller
56 have to use a "gpio-ranges" entry.
57 More details in Documentation/devicetree/bindings/gpio/gpio.txt.
60 #include <dt-bindings/pinctrl/stm32f429-pinfunc.h>
66 compatible = "st,stm32f429-pinctrl";
67 ranges = <0 0x40020000 0x3000>;
70 gpioa: gpio@40020000 {
74 resets = <&reset_ahb1 0>;
75 st,bank-name = "GPIOA";
78 pin-functions nodes follow...
82 #include <dt-bindings/pinctrl/stm32f429-pinfunc.h>
85 pinctrl: pin-controller {
88 compatible = "st,stm32f429-pinctrl";
89 ranges = <0 0x40020000 0x3000>;
92 gpioa: gpio@40020000 {
96 resets = <&reset_ahb1 0>;
97 st,bank-name = "GPIOA";
98 gpio-ranges = <&pinctrl 0 0 16>;
101 gpiob: gpio@40020400 {
105 resets = <&reset_ahb1 0>;
106 st,bank-name = "GPIOB";
108 gpio-ranges = <&pinctrl 0 16 3>,
114 pin-functions nodes follow...
118 Contents of function subnode node:
119 ----------------------------------
121 A pinctrl node should contain at least one subnode representing the
122 pinctrl group available on the machine. Each subnode will list the
123 pins it needs, and how they should be configured, with regard to muxer
124 configuration, pullups, drive, output high/low and output speed.
127 pinmux = <PIN_NUMBER_PINMUX>;
132 - pinmux: integer array, represents gpio pin number and mux setting.
133 Supported pin number and mux varies for different SoCs, and are defined in
134 dt-bindings/pinctrl/<soc>-pinfunc.h directly.
135 These defines are calculated as:
136 ((port * 16 + line) << 8) | function
138 - port: The gpio port index (PA = 0, PB = 1, ..., PK = 11)
139 - line: The line offset within the port (PA0 = 0, PA1 = 1, ..., PA15 = 15)
140 - function: The function number, can be:
142 * 1 : Alternate Function 0
143 * 2 : Alternate Function 1
144 * 3 : Alternate Function 2
146 * 16 : Alternate Function 15
149 To simplify the usage, macro is available to generate "pinmux" field.
150 This macro is available here:
151 - include/dt-bindings/pinctrl/stm32-pinfunc.h
153 Some examples of using macro:
154 /* GPIO A9 set as alernate function 2 */
156 pinmux = <STM32_PINMUX('A', 9, AF2)>;
158 /* GPIO A9 set as GPIO */
160 pinmux = <STM32_PINMUX('A', 9, GPIO)>;
162 /* GPIO A9 set as analog */
164 pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
168 - GENERIC_PINCONFIG: is the generic pinconfig options to use.
169 Available options are:
177 - slew-rate = <x>, with x being:
187 usart1_pins_a: usart1@0 {
189 pinmux = <STM32_PINMUX('A', 9, AF7)>;
195 pinmux = <STM32_PINMUX('A', 10, AF7)>;
202 pinctrl-0 = <&usart1_pins_a>;
203 pinctrl-names = "default";