Documentation/devicetree/bindings/pinctrl/pinctrl-mt7622.txt

   1 == MediaTek MT7622 pinctrl controller ==
   2
   3 Required properties for the root node:
   4  - compatible: Should be one of the following
   5                "mediatek,mt7622-pinctrl" for MT7622 SoC
   6  - reg: offset and length of the pinctrl space
   7
   8  - gpio-controller: Marks the device node as a GPIO controller.
   9  - #gpio-cells: Should be two. The first cell is the pin number and the
  10    second is the GPIO flags.
  11
  12 Optional properties:
  13 - interrupt-controller  : Marks the device node as an interrupt controller
  14
  15 If the property interrupt-controller is defined, following property is required
  16 - reg-names: A string describing the "reg" entries. Must contain "eint".
  17 - interrupts : The interrupt output from the controller.
  18 - #interrupt-cells: Should be two.
  19 - interrupt-parent: Phandle of the interrupt parent to which the external
  20   GPIO interrupts are forwarded to.
  21
  22 Please refer to pinctrl-bindings.txt in this directory for details of the
  23 common pinctrl bindings used by client devices, including the meaning of the
  24 phrase "pin configuration node".
  25
  26 MT7622 pin configuration nodes act as a container for an arbitrary number of
  27 subnodes. Each of these subnodes represents some desired configuration for a
  28 pin, a group, or a list of pins or groups. This configuration can include the
  29 mux function to select on those pin(s)/group(s), and various pin configuration
  30 parameters, such as pull-up, slew rate, etc.
  31
  32 We support 2 types of configuration nodes. Those nodes can be either pinmux
  33 nodes or pinconf nodes. Each configuration node can consist of multiple nodes
  34 describing the pinmux and pinconf options.
  35
  36 The name of each subnode doesn't matter as long as it is unique; all subnodes
  37 should be enumerated and processed purely based on their content.
  38
  39 == pinmux nodes content ==
  40
  41 The following generic properties as defined in pinctrl-bindings.txt are valid
  42 to specify in a pinmux subnode:
  43
  44 Required properties are:
  45  - groups: An array of strings. Each string contains the name of a group.
  46   Valid values for these names are listed below.
  47  - function: A string containing the name of the function to mux to the
  48   group. Valid values for function names are listed below.
  49
  50 == pinconf nodes content ==
  51
  52 The following generic properties as defined in pinctrl-bindings.txt are valid
  53 to specify in a pinconf subnode:
  54
  55 Required properties are:
  56  - pins: An array of strings. Each string contains the name of a pin.
  57   Valid values for these names are listed below.
  58  - groups: An array of strings. Each string contains the name of a group.
  59   Valid values for these names are listed below.
  60
  61 Optional properies are:
  62  bias-disable, bias-pull, bias-pull-down, input-enable,
  63  input-schmitt-enable, input-schmitt-disable, output-enable
  64  output-low, output-high, drive-strength, slew-rate
  65
  66  Valid arguments for 'slew-rate' are '0' for no slew rate controlled and '1' for
  67  slower slew rate respectively.
  68  Valid arguments for 'drive-strength', 4, 8, 12, or 16 in mA.
  69
  70 The following specific properties as defined are valid to specify in a pinconf
  71 subnode:
  72
  73 Optional properties are:
  74  - mediatek,tdsel: An integer describing the steps for output level shifter duty
  75    cycle when asserted (high pulse width adjustment). Valid arguments are from 0
  76    to 15.
  77  - mediatek,rdsel: An integer describing the steps for input level shifter duty
  78    cycle when asserted (high pulse width adjustment). Valid arguments are from 0
  79    to 63.
  80
  81 == Valid values for pins, function and groups on MT7622 ==
  82
  83 Valid values for pins are:
  84 pins can be referenced via the pin names as the below table shown and the
  85 related physical number is also put ahead of those names which helps cross
  86 references to pins between groups to know whether pins assignment conflict
  87 happens among devices try to acquire those available pins.
  88
  89         Pin #:  Valid values for pins
  90         -----------------------------
  91         PIN 0: "GPIO_A"
  92         PIN 1: "I2S1_IN"
  93         PIN 2: "I2S1_OUT"
  94         PIN 3: "I2S_BCLK"
  95         PIN 4: "I2S_WS"
  96         PIN 5: "I2S_MCLK"
  97         PIN 6: "TXD0"
  98         PIN 7: "RXD0"
  99         PIN 8: "SPI_WP"
 100         PIN 9: "SPI_HOLD"
 101         PIN 10: "SPI_CLK"
 102         PIN 11: "SPI_MOSI"
 103         PIN 12: "SPI_MISO"
 104         PIN 13: "SPI_CS"
 105         PIN 14: "I2C_SDA"
 106         PIN 15: "I2C_SCL"
 107         PIN 16: "I2S2_IN"
 108         PIN 17: "I2S3_IN"
 109         PIN 18: "I2S4_IN"
 110         PIN 19: "I2S2_OUT"
 111         PIN 20: "I2S3_OUT"
 112         PIN 21: "I2S4_OUT"
 113         PIN 22: "GPIO_B"
 114         PIN 23: "MDC"
 115         PIN 24: "MDIO"
 116         PIN 25: "G2_TXD0"
 117         PIN 26: "G2_TXD1"
 118         PIN 27: "G2_TXD2"
 119         PIN 28: "G2_TXD3"
 120         PIN 29: "G2_TXEN"
 121         PIN 30: "G2_TXC"
 122         PIN 31: "G2_RXD0"
 123         PIN 32: "G2_RXD1"
 124         PIN 33: "G2_RXD2"
 125         PIN 34: "G2_RXD3"
 126         PIN 35: "G2_RXDV"
 127         PIN 36: "G2_RXC"
 128         PIN 37: "NCEB"
 129         PIN 38: "NWEB"
 130         PIN 39: "NREB"
 131         PIN 40: "NDL4"
 132         PIN 41: "NDL5"
 133         PIN 42: "NDL6"
 134         PIN 43: "NDL7"
 135         PIN 44: "NRB"
 136         PIN 45: "NCLE"
 137         PIN 46: "NALE"
 138         PIN 47: "NDL0"
 139         PIN 48: "NDL1"
 140         PIN 49: "NDL2"
 141         PIN 50: "NDL3"
 142         PIN 51: "MDI_TP_P0"
 143         PIN 52: "MDI_TN_P0"
 144         PIN 53: "MDI_RP_P0"
 145         PIN 54: "MDI_RN_P0"
 146         PIN 55: "MDI_TP_P1"
 147         PIN 56: "MDI_TN_P1"
 148         PIN 57: "MDI_RP_P1"
 149         PIN 58: "MDI_RN_P1"
 150         PIN 59: "MDI_RP_P2"
 151         PIN 60: "MDI_RN_P2"
 152         PIN 61: "MDI_TP_P2"
 153         PIN 62: "MDI_TN_P2"
 154         PIN 63: "MDI_TP_P3"
 155         PIN 64: "MDI_TN_P3"
 156         PIN 65: "MDI_RP_P3"
 157         PIN 66: "MDI_RN_P3"
 158         PIN 67: "MDI_RP_P4"
 159         PIN 68: "MDI_RN_P4"
 160         PIN 69: "MDI_TP_P4"
 161         PIN 70: "MDI_TN_P4"
 162         PIN 71: "PMIC_SCL"
 163         PIN 72: "PMIC_SDA"
 164         PIN 73: "SPIC1_CLK"
 165         PIN 74: "SPIC1_MOSI"
 166         PIN 75: "SPIC1_MISO"
 167         PIN 76: "SPIC1_CS"
 168         PIN 77: "GPIO_D"
 169         PIN 78: "WATCHDOG"
 170         PIN 79: "RTS3_N"
 171         PIN 80: "CTS3_N"
 172         PIN 81: "TXD3"
 173         PIN 82: "RXD3"
 174         PIN 83: "PERST0_N"
 175         PIN 84: "PERST1_N"
 176         PIN 85: "WLED_N"
 177         PIN 86: "EPHY_LED0_N"
 178         PIN 87: "AUXIN0"
 179         PIN 88: "AUXIN1"
 180         PIN 89: "AUXIN2"
 181         PIN 90: "AUXIN3"
 182         PIN 91: "TXD4"
 183         PIN 92: "RXD4"
 184         PIN 93: "RTS4_N"
 185         PIN 94: "CST4_N"
 186         PIN 95: "PWM1"
 187         PIN 96: "PWM2"
 188         PIN 97: "PWM3"
 189         PIN 98: "PWM4"
 190         PIN 99: "PWM5"
 191         PIN 100: "PWM6"
 192         PIN 101: "PWM7"
 193         PIN 102: "GPIO_E"
 194
 195 Valid values for function are:
 196         "emmc", "eth", "i2c", "i2s", "ir", "led", "flash", "pcie",
 197         "pmic", "pwm", "sd", "spi", "tdm", "uart", "watchdog"
 198
 199 Valid values for groups are:
 200 additional data is put followingly with valid value allowing us to know which
 201 applicable function and which relevant pins (in pin#) are able applied for that
 202 group.
 203
 204         Valid value                     function        pins (in pin#)
 205         -------------------------------------------------------------------------
 206         "emmc"                          "emmc"          40, 41, 42, 43, 44, 45,
 207                                                         47, 48, 49, 50
 208         "emmc_rst"                      "emmc"          37
 209         "esw"                           "eth"           51, 52, 53, 54, 55, 56,
 210                                                         57, 58, 59, 60, 61, 62,
 211                                                         63, 64, 65, 66, 67, 68,
 212                                                         69, 70
 213         "esw_p0_p1"                     "eth"           51, 52, 53, 54, 55, 56,
 214                                                         57, 58
 215         "esw_p2_p3_p4"                  "eth"           59, 60, 61, 62, 63, 64,
 216                                                         65, 66, 67, 68, 69, 70
 217         "rgmii_via_esw"                 "eth"           59, 60, 61, 62, 63, 64,
 218                                                         65, 66, 67, 68, 69, 70
 219         "rgmii_via_gmac1"               "eth"           59, 60, 61, 62, 63, 64,
 220                                                         65, 66, 67, 68, 69, 70
 221         "rgmii_via_gmac2"               "eth"           25, 26, 27, 28, 29, 30,
 222                                                         31, 32, 33, 34, 35, 36
 223         "mdc_mdio"                      "eth"           23, 24
 224         "i2c0"                          "i2c"           14, 15
 225         "i2c1_0"                        "i2c"           55, 56
 226         "i2c1_1"                        "i2c"           73, 74
 227         "i2c1_2"                        "i2c"           87, 88
 228         "i2c2_0"                        "i2c"           57, 58
 229         "i2c2_1"                        "i2c"           75, 76
 230         "i2c2_2"                        "i2c"           89, 90
 231         "i2s_in_mclk_bclk_ws"           "i2s"           3, 4, 5
 232         "i2s1_in_data"                  "i2s"           1
 233         "i2s2_in_data"                  "i2s"           16
 234         "i2s3_in_data"                  "i2s"           17
 235         "i2s4_in_data"                  "i2s"           18
 236         "i2s_out_mclk_bclk_ws"          "i2s"           3, 4, 5
 237         "i2s1_out_data"                 "i2s"           2
 238         "i2s2_out_data"                 "i2s"           19
 239         "i2s3_out_data"                 "i2s"           20
 240         "i2s4_out_data"                 "i2s"           21
 241         "ir_0_tx"                       "ir"            16
 242         "ir_1_tx"                       "ir"            59
 243         "ir_2_tx"                       "ir"            99
 244         "ir_0_rx"                       "ir"            17
 245         "ir_1_rx"                       "ir"            60
 246         "ir_2_rx"                       "ir"            100
 247         "ephy_leds"                     "led"           86, 91, 92, 93, 94
 248         "ephy0_led"                     "led"           86
 249         "ephy1_led"                     "led"           91
 250         "ephy2_led"                     "led"           92
 251         "ephy3_led"                     "led"           93
 252         "ephy4_led"                     "led"           94
 253         "wled"                          "led"           85
 254         "par_nand"                      "flash"         37, 38, 39, 40, 41, 42,
 255                                                         43, 44, 45, 46, 47, 48,
 256                                                         49, 50
 257         "snfi"                          "flash"         8, 9, 10, 11, 12, 13
 258         "spi_nor"                       "flash"         8, 9, 10, 11, 12, 13
 259         "pcie0_0_waken"                 "pcie"          14
 260         "pcie0_1_waken"                 "pcie"          79
 261         "pcie1_0_waken"                 "pcie"          14
 262         "pcie0_0_clkreq"                "pcie"          15
 263         "pcie0_1_clkreq"                "pcie"          80
 264         "pcie1_0_clkreq"                "pcie"          15
 265         "pcie0_pad_perst"               "pcie"          83
 266         "pcie1_pad_perst"               "pcie"          84
 267         "pmic_bus"                      "pmic"          71, 72
 268         "pwm_ch1_0"                     "pwm"           51
 269         "pwm_ch1_1"                     "pwm"           73
 270         "pwm_ch1_2"                     "pwm"           95
 271         "pwm_ch2_0"                     "pwm"           52
 272         "pwm_ch2_1"                     "pwm"           74
 273         "pwm_ch2_2"                     "pwm"           96
 274         "pwm_ch3_0"                     "pwm"           53
 275         "pwm_ch3_1"                     "pwm"           75
 276         "pwm_ch3_2"                     "pwm"           97
 277         "pwm_ch4_0"                     "pwm"           54
 278         "pwm_ch4_1"                     "pwm"           67
 279         "pwm_ch4_2"                     "pwm"           76
 280         "pwm_ch4_3"                     "pwm"           98
 281         "pwm_ch5_0"                     "pwm"           68
 282         "pwm_ch5_1"                     "pwm"           77
 283         "pwm_ch5_2"                     "pwm"           99
 284         "pwm_ch6_0"                     "pwm"           69
 285         "pwm_ch6_1"                     "pwm"           78
 286         "pwm_ch6_2"                     "pwm"           81
 287         "pwm_ch6_3"                     "pwm"           100
 288         "pwm_ch7_0"                     "pwm"           70
 289         "pwm_ch7_1"                     "pwm"           82
 290         "pwm_ch7_2"                     "pwm"           101
 291         "sd_0"                          "sd"            16, 17, 18, 19, 20, 21
 292         "sd_1"                          "sd"            25, 26, 27, 28, 29, 30
 293         "spic0_0"                       "spi"           63, 64, 65, 66
 294         "spic0_1"                       "spi"           79, 80, 81, 82
 295         "spic1_0"                       "spi"           67, 68, 69, 70
 296         "spic1_1"                       "spi"           73, 74, 75, 76
 297         "spic2_0_wp_hold"               "spi"           8, 9
 298         "spic2_0"                       "spi"           10, 11, 12, 13
 299         "tdm_0_out_mclk_bclk_ws"        "tdm"           8, 9, 10
 300         "tdm_0_in_mclk_bclk_ws"         "tdm"           11, 12, 13
 301         "tdm_0_out_data"                "tdm"           20
 302         "tdm_0_in_data"                 "tdm"           21
 303         "tdm_1_out_mclk_bclk_ws"        "tdm"           57, 58, 59
 304         "tdm_1_in_mclk_bclk_ws"         "tdm"           60, 61, 62
 305         "tdm_1_out_data"                "tdm"           55
 306         "tdm_1_in_data"                 "tdm"           56
 307         "uart0_0_tx_rx"                 "uart"          6, 7
 308         "uart1_0_tx_rx"                 "uart"          55, 56
 309         "uart1_0_rts_cts"               "uart"          57, 58
 310         "uart1_1_tx_rx"                 "uart"          73, 74
 311         "uart1_1_rts_cts"               "uart"          75, 76
 312         "uart2_0_tx_rx"                 "uart"          3, 4
 313         "uart2_0_rts_cts"               "uart"          1, 2
 314         "uart2_1_tx_rx"                 "uart"          51, 52
 315         "uart2_1_rts_cts"               "uart"          53, 54
 316         "uart2_2_tx_rx"                 "uart"          59, 60
 317         "uart2_2_rts_cts"               "uart"          61, 62
 318         "uart2_3_tx_rx"                 "uart"          95, 96
 319         "uart3_0_tx_rx"                 "uart"          57, 58
 320         "uart3_1_tx_rx"                 "uart"          81, 82
 321         "uart3_1_rts_cts"               "uart"          79, 80
 322         "uart4_0_tx_rx"                 "uart"          61, 62
 323         "uart4_1_tx_rx"                 "uart"          91, 92
 324         "uart4_1_rts_cts"               "uart"          93, 94
 325         "uart4_2_tx_rx"                 "uart"          97, 98
 326         "uart4_2_rts_cts"               "uart"          95, 96
 327         "watchdog"                      "watchdog"      78
 328
 329 Example:
 330
 331         pio: pinctrl@10211000 {
 332                 compatible = "mediatek,mt7622-pinctrl";
 333                 reg = <0 0x10211000 0 0x1000>;
 334                 gpio-controller;
 335                 #gpio-cells = <2>;
 336
 337                 pinctrl_eth_default: eth-default {
 338                         mux-mdio {
 339                                 groups = "mdc_mdio";
 340                                 function = "eth";
 341                                 drive-strength = <12>;
 342                         };
 343
 344                         mux-gmac2 {
 345                                 groups = "gmac2";
 346                                 function = "eth";
 347                                 drive-strength = <12>;
 348                         };
 349
 350                         mux-esw {
 351                                 groups = "esw";
 352                                 function = "eth";
 353                                 drive-strength = <8>;
 354                         };
 355
 356                         conf-mdio {
 357                                 pins = "MDC";
 358                                 bias-pull-up;
 359                         };
 360                 };
 361         };