Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt

   1 ======================
   2 Aspeed Pin Controllers
   3 ======================
   4
   5 The Aspeed SoCs vary in functionality inside a generation but have a common mux
   6 device register layout.
   7
   8 Required properties for g4:
   9 - compatible :                  Should be one of the following:
  10                                 "aspeed,ast2400-pinctrl"
  11                                 "aspeed,g4-pinctrl"
  12
  13 Required properties for g5:
  14 - compatible :                  Should be one of the following:
  15                                 "aspeed,ast2500-pinctrl"
  16                                 "aspeed,g5-pinctrl"
  17
  18 - aspeed,external-nodes:        A cell of phandles to external controller nodes:
  19                                 0: compatible with "aspeed,ast2500-gfx", "syscon"
  20                                 1: compatible with "aspeed,ast2500-lhc", "syscon"
  21
  22 The pin controller node should be the child of a syscon node with the required
  23 property:
  24
  25 - compatible :          Should be one of the following:
  26                         "aspeed,ast2400-scu", "syscon", "simple-mfd"
  27                         "aspeed,g4-scu", "syscon", "simple-mfd"
  28                         "aspeed,ast2500-scu", "syscon", "simple-mfd"
  29                         "aspeed,g5-scu", "syscon", "simple-mfd"
  30
  31 Refer to the the bindings described in
  32 Documentation/devicetree/bindings/mfd/syscon.txt
  33
  34 Subnode Format
  35 ==============
  36
  37 The required properties of child nodes are (as defined in pinctrl-bindings):
  38 - function
  39 - groups
  40
  41 Each function has only one associated pin group. Each group is named by its
  42 function. The following values for the function and groups properties are
  43 supported:
  44
  45 aspeed,ast2400-pinctrl, aspeed,g4-pinctrl:
  46
  47 ACPI ADC0 ADC1 ADC10 ADC11 ADC12 ADC13 ADC14 ADC15 ADC2 ADC3 ADC4 ADC5 ADC6
  48 ADC7 ADC8 ADC9 BMCINT DDCCLK DDCDAT EXTRST FLACK FLBUSY FLWP GPID GPID0 GPID2
  49 GPID4 GPID6 GPIE0 GPIE2 GPIE4 GPIE6 I2C10 I2C11 I2C12 I2C13 I2C14 I2C3 I2C4
  50 I2C5 I2C6 I2C7 I2C8 I2C9 LPCPD LPCPME LPCRST LPCSMI MAC1LINK MAC2LINK MDIO1
  51 MDIO2 NCTS1 NCTS2 NCTS3 NCTS4 NDCD1 NDCD2 NDCD3 NDCD4 NDSR1 NDSR2 NDSR3 NDSR4
  52 NDTR1 NDTR2 NDTR3 NDTR4 NDTS4 NRI1 NRI2 NRI3 NRI4 NRTS1 NRTS2 NRTS3 OSCCLK PWM0
  53 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 RGMII1 RGMII2 RMII1 RMII2 ROM16 ROM8 ROMCS1
  54 ROMCS2 ROMCS3 ROMCS4 RXD1 RXD2 RXD3 RXD4 SALT1 SALT2 SALT3 SALT4 SD1 SD2 SGPMCK
  55 SGPMI SGPMLD SGPMO SGPSCK SGPSI0 SGPSI1 SGPSLD SIOONCTRL SIOPBI SIOPBO SIOPWREQ
  56 SIOPWRGD SIOS3 SIOS5 SIOSCI SPI1 SPI1DEBUG SPI1PASSTHRU SPICS1 TIMER3 TIMER4
  57 TIMER5 TIMER6 TIMER7 TIMER8 TXD1 TXD2 TXD3 TXD4 UART6 USBCKI VGABIOS_ROM VGAHS
  58 VGAVS VPI18 VPI24 VPI30 VPO12 VPO24 WDTRST1 WDTRST2
  59
  60 aspeed,ast2500-pinctrl, aspeed,g5-pinctrl:
  61
  62 ACPI ADC0 ADC1 ADC10 ADC11 ADC12 ADC13 ADC14 ADC15 ADC2 ADC3 ADC4 ADC5 ADC6
  63 ADC7 ADC8 ADC9 BMCINT DDCCLK DDCDAT ESPI FWSPICS1 FWSPICS2 GPID0 GPID2 GPID4
  64 GPID6 GPIE0 GPIE2 GPIE4 GPIE6 I2C10 I2C11 I2C12 I2C13 I2C14 I2C3 I2C4 I2C5 I2C6
  65 I2C7 I2C8 I2C9 LAD0 LAD1 LAD2 LAD3 LCLK LFRAME LPCHC LPCPD LPCPLUS LPCPME
  66 LPCRST LPCSMI LSIRQ MAC1LINK MAC2LINK MDIO1 MDIO2 NCTS1 NCTS2 NCTS3 NCTS4 NDCD1
  67 NDCD2 NDCD3 NDCD4 NDSR1 NDSR2 NDSR3 NDSR4 NDTR1 NDTR2 NDTR3 NDTR4 NRI1 NRI2
  68 NRI3 NRI4 NRTS1 NRTS2 NRTS3 NRTS4 OSCCLK PEWAKE PNOR PWM0 PWM1 PWM2 PWM3 PWM4
  69 PWM5 PWM6 PWM7 RGMII1 RGMII2 RMII1 RMII2 RXD1 RXD2 RXD3 RXD4 SALT1 SALT10
  70 SALT11 SALT12 SALT13 SALT14 SALT2 SALT3 SALT4 SALT5 SALT6 SALT7 SALT8 SALT9
  71 SCL1 SCL2 SD1 SD2 SDA1 SDA2 SGPS1 SGPS2 SIOONCTRL SIOPBI SIOPBO SIOPWREQ
  72 SIOPWRGD SIOS3 SIOS5 SIOSCI SPI1 SPI1CS1 SPI1DEBUG SPI1PASSTHRU SPI2CK SPI2CS0
  73 SPI2CS1 SPI2MISO SPI2MOSI TIMER3 TIMER4 TIMER5 TIMER6 TIMER7 TIMER8 TXD1 TXD2
  74 TXD3 TXD4 UART6 USBCKI VGABIOSROM VGAHS VGAVS VPI24 VPO WDTRST1 WDTRST2
  75
  76 Examples
  77 ========
  78
  79 g4 Example
  80 ----------
  81
  82 syscon: scu@1e6e2000 {
  83         compatible = "aspeed,ast2400-scu", "syscon", "simple-mfd";
  84         reg = <0x1e6e2000 0x1a8>;
  85
  86         pinctrl: pinctrl {
  87                 compatible = "aspeed,g4-pinctrl";
  88
  89                 pinctrl_i2c3_default: i2c3_default {
  90                         function = "I2C3";
  91                         groups = "I2C3";
  92                 };
  93         };
  94 };
  95
  96 g5 Example
  97 ----------
  98
  99 ahb {
 100         apb {
 101                 syscon: scu@1e6e2000 {
 102                         compatible = "aspeed,ast2500-scu", "syscon", "simple-mfd";
 103                         reg = <0x1e6e2000 0x1a8>;
 104
 105                         pinctrl: pinctrl {
 106                                 compatible = "aspeed,g5-pinctrl";
 107                                 aspeed,external-nodes = <&gfx &lhc>;
 108
 109                                 pinctrl_i2c3_default: i2c3_default {
 110                                         function = "I2C3";
 111                                         groups = "I2C3";
 112                                 };
 113                         };
 114                 };
 115
 116                 gfx: display@1e6e6000 {
 117                         compatible = "aspeed,ast2500-gfx", "syscon";
 118                         reg = <0x1e6e6000 0x1000>;
 119                 };
 120         };
 121
 122         lpc: lpc@1e789000 {
 123                 compatible = "aspeed,ast2500-lpc", "simple-mfd";
 124                 reg = <0x1e789000 0x1000>;
 125
 126                 #address-cells = <1>;
 127                 #size-cells = <1>;
 128                 ranges = <0x0 0x1e789000 0x1000>;
 129
 130                 lpc_host: lpc-host@80 {
 131                         compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon";
 132                         reg = <0x80 0x1e0>;
 133                         reg-io-width = <4>;
 134
 135                         #address-cells = <1>;
 136                         #size-cells = <1>;
 137                         ranges = <0x0 0x80 0x1e0>;
 138
 139                         lhc: lhc@20 {
 140                                compatible = "aspeed,ast2500-lhc";
 141                                reg = <0x20 0x24 0x48 0x8>;
 142                         };
 143                 };
 144         };
 145 };
 146
 147 Please refer to pinctrl-bindings.txt in this directory for details of the
 148 common pinctrl bindings used by client devices.