1 * Allwinner A1X Pin Controller
3 The pins controlled by sunXi pin controller are organized in banks,
4 each bank has 32 pins. Each pin has 7 multiplexing functions, with
5 the first two functions being GPIO in and out. The configuration on
6 the pins includes drive strength and pull-up.
9 - compatible: Should be one of the following (depending on your SoC):
10 "allwinner,sun4i-a10-pinctrl"
11 "allwinner,sun5i-a10s-pinctrl"
12 "allwinner,sun5i-a13-pinctrl"
13 "allwinner,sun6i-a31-pinctrl"
14 "allwinner,sun6i-a31s-pinctrl"
15 "allwinner,sun6i-a31-r-pinctrl"
16 "allwinner,sun7i-a20-pinctrl"
17 "allwinner,sun8i-a23-pinctrl"
18 "allwinner,sun8i-a23-r-pinctrl"
19 "allwinner,sun8i-a33-pinctrl"
20 "allwinner,sun9i-a80-pinctrl"
21 "allwinner,sun9i-a80-r-pinctrl"
22 "allwinner,sun8i-a83t-pinctrl"
23 "allwinner,sun8i-a83t-r-pinctrl"
24 "allwinner,sun8i-h3-pinctrl"
25 "allwinner,sun8i-h3-r-pinctrl"
26 "allwinner,sun8i-r40-pinctrl"
27 "allwinner,sun50i-a64-pinctrl"
28 "allwinner,sun50i-a64-r-pinctrl"
29 "allwinner,sun50i-h5-pinctrl"
30 "allwinner,sun50i-h6-pinctrl"
31 "allwinner,sun50i-h6-r-pinctrl"
32 "allwinner,suniv-f1c100s-pinctrl"
33 "nextthing,gr8-pinctrl"
35 - reg: Should contain the register physical address and length for the
38 - clocks: phandle to the clocks feeding the pin controller:
39 - "apb": the gated APB parent clock
40 - "hosc": the high frequency oscillator in the system
41 - "losc": the low frequency oscillator in the system
43 Note: For backward compatibility reasons, the hosc and losc clocks are only
44 required if you need to use the optional input-debounce property. Any new
45 device tree should set them.
47 Each pin bank, depending on the SoC, can have an associated regulator:
49 - vcc-pa-supply: for the A10, A20, A31, A31s, A80 and R40 SoCs
50 - vcc-pb-supply: for the A31, A31s, A80 and V3s SoCs
51 - vcc-pc-supply: for the A10, A20, A31, A31s, A64, A80, H5, R40 and V3s SoCs
52 - vcc-pd-supply: for the A23, A31, A31s, A64, A80, A83t, H3, H5 and R40 SoCs
53 - vcc-pe-supply: for the A10, A20, A31, A31s, A64, A80, R40 and V3s SoCs
54 - vcc-pf-supply: for the A10, A20, A31, A31s, A80, R40 and V3s SoCs
55 - vcc-pg-supply: for the A10, A20, A31, A31s, A64, A80, H3, H5, R40 and V3s SoCs
56 - vcc-ph-supply: for the A31, A31s and A80 SoCs
57 - vcc-pl-supply: for the r-pinctrl of the A64, A80 and A83t SoCs
58 - vcc-pm-supply: for the r-pinctrl of the A31, A31s and A80 SoCs
61 - input-debounce: Array of debouncing periods in microseconds. One period per
62 irq bank found in the controller. 0 if no setup required.
65 Please refer to pinctrl-bindings.txt in this directory for details of the
66 common pinctrl bindings used by client devices.
68 A pinctrl node should contain at least one subnodes representing the
69 pinctrl groups available on the machine. Each subnode will list the
70 pins it needs, and how they should be configured, with regard to muxer
71 configuration, drive strength and pullups. If one of these options is
72 not set, its actual value will be unspecified.
74 Allwinner A1X Pin Controller supports the generic pin multiplexing and
75 configuration bindings. For details on each properties, you can refer to
76 ./pinctrl-bindings.txt.
78 Required sub-node properties:
82 Optional sub-node properties:
88 *** Deprecated pin configuration and multiplexing binding
90 Required subnode-properties:
92 - allwinner,pins: List of strings containing the pin name.
93 - allwinner,function: Function to mux the pins listed above to.
95 Optional subnode-properties:
96 - allwinner,drive: Integer. Represents the current sent to the pin
101 - allwinner,pull: Integer.
104 2: Pull-down resistor
108 pio: pinctrl@1c20800 {
109 compatible = "allwinner,sun5i-a13-pinctrl";
110 reg = <0x01c20800 0x400>;
111 #address-cells = <1>;
114 uart1_pins_a: uart1@0 {
115 allwinner,pins = "PE10", "PE11";
116 allwinner,function = "uart1";
117 allwinner,drive = <0>;
118 allwinner,pull = <0>;
121 uart1_pins_b: uart1@1 {
122 allwinner,pins = "PG3", "PG4";
123 allwinner,function = "uart1";
124 allwinner,drive = <0>;
125 allwinner,pull = <0>;
130 GPIO and interrupt controller
131 -----------------------------
133 This hardware also acts as a GPIO controller and an interrupt
136 Consumers that would want to refer to one or the other (or both)
137 should provide through the usual *-gpios and interrupts properties a
138 cell with 3 arguments, first the number of the bank, then the pin
139 inside that bank, and finally the flags for the GPIO/interrupts.
144 compatible = "nxp,pcf8574a";
150 interrupt-parent = <&pio>;
151 interrupts = <6 0 IRQ_TYPE_EDGE_FALLING>;
152 interrupt-controller;
153 #interrupt-cells = <2>;
156 reg_usb1_vbus: usb1-vbus {
157 compatible = "regulator-fixed";
158 regulator-name = "usb1-vbus";
159 regulator-min-microvolt = <5000000>;
160 regulator-max-microvolt = <5000000>;
161 gpio = <&pio 7 6 GPIO_ACTIVE_HIGH>;