1 * Allwinner A1X Pin Controller
3 The pins controlled by sunXi pin controller are organized in banks,
4 each bank has 32 pins. Each pin has 7 multiplexing functions, with
5 the first two functions being GPIO in and out. The configuration on
6 the pins includes drive strength and pull-up.
9 - compatible: Should be one of the following (depending on your SoC):
10 "allwinner,sun4i-a10-pinctrl"
11 "allwinner,sun5i-a10s-pinctrl"
12 "allwinner,sun5i-a13-pinctrl"
13 "allwinner,sun6i-a31-pinctrl"
14 "allwinner,sun6i-a31s-pinctrl"
15 "allwinner,sun6i-a31-r-pinctrl"
16 "allwinner,sun7i-a20-pinctrl"
17 "allwinner,sun8i-a23-pinctrl"
18 "allwinner,sun8i-a23-r-pinctrl"
19 "allwinner,sun8i-a33-pinctrl"
20 "allwinner,sun9i-a80-pinctrl"
21 "allwinner,sun9i-a80-r-pinctrl"
22 "allwinner,sun8i-a83t-pinctrl"
23 "allwinner,sun8i-a83t-r-pinctrl"
24 "allwinner,sun8i-h3-pinctrl"
25 "allwinner,sun8i-h3-r-pinctrl"
26 "allwinner,sun8i-r40-pinctrl"
27 "allwinner,sun8i-v3-pinctrl"
28 "allwinner,sun8i-v3s-pinctrl"
29 "allwinner,sun50i-a64-pinctrl"
30 "allwinner,sun50i-a64-r-pinctrl"
31 "allwinner,sun50i-h5-pinctrl"
32 "allwinner,sun50i-h6-pinctrl"
33 "allwinner,sun50i-h6-r-pinctrl"
34 "allwinner,suniv-f1c100s-pinctrl"
35 "nextthing,gr8-pinctrl"
37 - reg: Should contain the register physical address and length for the
40 - clocks: phandle to the clocks feeding the pin controller:
41 - "apb": the gated APB parent clock
42 - "hosc": the high frequency oscillator in the system
43 - "losc": the low frequency oscillator in the system
45 Note: For backward compatibility reasons, the hosc and losc clocks are only
46 required if you need to use the optional input-debounce property. Any new
47 device tree should set them.
49 Each pin bank, depending on the SoC, can have an associated regulator:
51 - vcc-pa-supply: for the A10, A20, A31, A31s, A80 and R40 SoCs
52 - vcc-pb-supply: for the A31, A31s, A80 and V3s SoCs
53 - vcc-pc-supply: for the A10, A20, A31, A31s, A64, A80, H5, R40 and V3s SoCs
54 - vcc-pd-supply: for the A23, A31, A31s, A64, A80, A83t, H3, H5 and R40 SoCs
55 - vcc-pe-supply: for the A10, A20, A31, A31s, A64, A80, R40 and V3s SoCs
56 - vcc-pf-supply: for the A10, A20, A31, A31s, A80, R40 and V3s SoCs
57 - vcc-pg-supply: for the A10, A20, A31, A31s, A64, A80, H3, H5, R40 and V3s SoCs
58 - vcc-ph-supply: for the A31, A31s and A80 SoCs
59 - vcc-pl-supply: for the r-pinctrl of the A64, A80 and A83t SoCs
60 - vcc-pm-supply: for the r-pinctrl of the A31, A31s and A80 SoCs
63 - input-debounce: Array of debouncing periods in microseconds. One period per
64 irq bank found in the controller. 0 if no setup required.
67 Please refer to pinctrl-bindings.txt in this directory for details of the
68 common pinctrl bindings used by client devices.
70 A pinctrl node should contain at least one subnodes representing the
71 pinctrl groups available on the machine. Each subnode will list the
72 pins it needs, and how they should be configured, with regard to muxer
73 configuration, drive strength and pullups. If one of these options is
74 not set, its actual value will be unspecified.
76 Allwinner A1X Pin Controller supports the generic pin multiplexing and
77 configuration bindings. For details on each properties, you can refer to
78 ./pinctrl-bindings.txt.
80 Required sub-node properties:
84 Optional sub-node properties:
90 *** Deprecated pin configuration and multiplexing binding
92 Required subnode-properties:
94 - allwinner,pins: List of strings containing the pin name.
95 - allwinner,function: Function to mux the pins listed above to.
97 Optional subnode-properties:
98 - allwinner,drive: Integer. Represents the current sent to the pin
103 - allwinner,pull: Integer.
106 2: Pull-down resistor
110 pio: pinctrl@1c20800 {
111 compatible = "allwinner,sun5i-a13-pinctrl";
112 reg = <0x01c20800 0x400>;
113 #address-cells = <1>;
116 uart1_pins_a: uart1@0 {
117 allwinner,pins = "PE10", "PE11";
118 allwinner,function = "uart1";
119 allwinner,drive = <0>;
120 allwinner,pull = <0>;
123 uart1_pins_b: uart1@1 {
124 allwinner,pins = "PG3", "PG4";
125 allwinner,function = "uart1";
126 allwinner,drive = <0>;
127 allwinner,pull = <0>;
132 GPIO and interrupt controller
133 -----------------------------
135 This hardware also acts as a GPIO controller and an interrupt
138 Consumers that would want to refer to one or the other (or both)
139 should provide through the usual *-gpios and interrupts properties a
140 cell with 3 arguments, first the number of the bank, then the pin
141 inside that bank, and finally the flags for the GPIO/interrupts.
146 compatible = "nxp,pcf8574a";
152 interrupt-parent = <&pio>;
153 interrupts = <6 0 IRQ_TYPE_EDGE_FALLING>;
154 interrupt-controller;
155 #interrupt-cells = <2>;
158 reg_usb1_vbus: usb1-vbus {
159 compatible = "regulator-fixed";
160 regulator-name = "usb1-vbus";
161 regulator-min-microvolt = <5000000>;
162 regulator-max-microvolt = <5000000>;
163 gpio = <&pio 7 6 GPIO_ACTIVE_HIGH>;