Documentation/devicetree/bindings/phy/uniphier-usb3-ssphy.txt

   1 Socionext UniPhier USB3 Super-Speed (SS) PHY
   2
   3 This describes the devicetree bindings for PHY interfaces built into
   4 USB3 controller implemented on Socionext UniPhier SoCs.
   5 Although the controller includes High-Speed PHY and Super-Speed PHY,
   6 this describes about Super-Speed PHY.
   7
   8 Required properties:
   9 - compatible: Should contain one of the following:
  10     "socionext,uniphier-pro4-usb3-ssphy" - for Pro4 SoC
  11     "socionext,uniphier-pxs2-usb3-ssphy" - for PXs2 SoC
  12     "socionext,uniphier-ld20-usb3-ssphy" - for LD20 SoC
  13     "socionext,uniphier-pxs3-usb3-ssphy" - for PXs3 SoC
  14 - reg: Specifies offset and length of the register set for the device.
  15 - #phy-cells: Should be 0.
  16 - clocks: A list of phandles to the clock gate for USB3 glue layer.
  17         According to the clock-names, appropriate clocks are required.
  18 - clock-names:
  19     "gio", "link" - for Pro4 SoC
  20     "phy", "phy-ext", "link" - for PXs3 SoC, "phy-ext" is optional.
  21     "phy", "link" - for others
  22 - resets: A list of phandles to the reset control for USB3 glue layer.
  23         According to the reset-names, appropriate resets are required.
  24 - reset-names:
  25     "gio", "link" - for Pro4 SoC
  26     "phy", "link" - for others
  27
  28 Optional properties:
  29 - vbus-supply: A phandle to the regulator for USB VBUS.
  30
  31 Refer to phy/phy-bindings.txt for the generic PHY binding properties.
  32
  33 Example:
  34
  35         usb-glue@65b00000 {
  36                 compatible = "socionext,uniphier-ld20-dwc3-glue",
  37                              "simple-mfd";
  38                 #address-cells = <1>;
  39                 #size-cells = <1>;
  40                 ranges = <0 0x65b00000 0x400>;
  41
  42                 usb_vbus0: regulator {
  43                         ...
  44                 };
  45
  46                 usb_ssphy0: ss-phy@300 {
  47                         compatible = "socionext,uniphier-ld20-usb3-ssphy";
  48                         reg = <0x300 0x10>;
  49                         #phy-cells = <0>;
  50                         clock-names = "link", "phy";
  51                         clocks = <&sys_clk 14>, <&sys_clk 16>;
  52                         reset-names = "link", "phy";
  53                         resets = <&sys_rst 14>, <&sys_rst 16>;
  54                         vbus-supply = <&usb_vbus0>;
  55                 };
  56                 ...
  57         };