1 Qualcomm QMP PHY controller
2 ===========================
4 QMP phy controller supports physical layer functionality for a number of
5 controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
8 - compatible: compatible list, contains:
9 "qcom,ipq8074-qmp-pcie-phy" for PCIe phy on IPQ8074
10 "qcom,msm8996-qmp-pcie-phy" for 14nm PCIe phy on msm8996,
11 "qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996,
12 "qcom,msm8998-qmp-usb3-phy" for USB3 QMP V3 phy on msm8998,
13 "qcom,sdm845-qmp-usb3-phy" for USB3 QMP V3 phy on sdm845,
14 "qcom,sdm845-qmp-usb3-uni-phy" for USB3 QMP V3 UNI phy on sdm845,
15 "qcom,sdm845-qmp-ufs-phy" for UFS QMP phy on sdm845.
18 - index 0: address and length of register set for PHY's common
20 - index 1: address and length of the DP_COM control block (for
21 "qcom,sdm845-qmp-usb3-phy" only).
24 - For "qcom,sdm845-qmp-usb3-phy":
25 - Should be: "reg-base", "dp_com"
27 - The reg-names property shouldn't be defined.
29 - #address-cells: must be 1
30 - #size-cells: must be 1
31 - ranges: must be present
33 - clocks: a list of phandles and clock-specifier pairs,
34 one for each entry in clock-names.
35 - clock-names: "cfg_ahb" for phy config clock,
36 "aux" for phy aux clock,
37 "ref" for 19.2 MHz ref clk,
38 "com_aux" for phy common block aux clock,
39 "ref_aux" for phy reference aux clock,
41 For "qcom,ipq8074-qmp-pcie-phy": no clocks are listed.
42 For "qcom,msm8996-qmp-pcie-phy" must contain:
43 "aux", "cfg_ahb", "ref".
44 For "qcom,msm8996-qmp-usb3-phy" must contain:
45 "aux", "cfg_ahb", "ref".
46 For "qcom,msm8998-qmp-usb3-phy" must contain:
47 "aux", "cfg_ahb", "ref".
48 For "qcom,sdm845-qmp-usb3-phy" must contain:
49 "aux", "cfg_ahb", "ref", "com_aux".
50 For "qcom,sdm845-qmp-usb3-uni-phy" must contain:
51 "aux", "cfg_ahb", "ref", "com_aux".
52 For "qcom,sdm845-qmp-ufs-phy" must contain:
55 - resets: a list of phandles and reset controller specifier pairs,
56 one for each entry in reset-names.
57 - reset-names: "phy" for reset of phy block,
58 "common" for phy common block reset,
59 "cfg" for phy's ahb cfg block reset.
61 For "qcom,ipq8074-qmp-pcie-phy" must contain:
63 For "qcom,msm8996-qmp-pcie-phy" must contain:
64 "phy", "common", "cfg".
65 For "qcom,msm8996-qmp-usb3-phy" must contain
67 For "qcom,msm8998-qmp-usb3-phy" must contain
69 For "qcom,sdm845-qmp-usb3-phy" must contain:
71 For "qcom,sdm845-qmp-usb3-uni-phy" must contain:
73 For "qcom,sdm845-qmp-ufs-phy": no resets are listed.
75 - vdda-phy-supply: Phandle to a regulator supply to PHY core block.
76 - vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block.
79 - vddp-ref-clk-supply: Phandle to a regulator supply to any specific refclk
83 - Each device node of QMP phy is required to have as many child nodes as
84 the number of lanes the PHY has.
86 Required properties for child nodes of PCIe PHYs (one child per lane):
87 - reg: list of offset and length pairs of register sets for PHY blocks -
88 tx, rx, pcs, and pcs_misc (optional).
89 - #phy-cells: must be 0
91 Required properties for a single "lanes" child node of non-PCIe PHYs:
92 - reg: list of offset and length pairs of register sets for PHY blocks
94 tx, rx, pcs, and (optionally) pcs_misc
96 tx0, rx0, pcs, tx1, rx1, and (optionally) pcs_misc
97 - #phy-cells: must be 0
99 Required properties for child node of PCIe and USB3 qmp phys:
100 - clocks: a list of phandles and clock-specifier pairs,
101 one for each entry in clock-names.
102 - clock-names: Must contain following:
103 "pipe<lane-number>" for pipe clock specific to each lane.
104 - clock-output-names: Name of the PHY clock that will be the parent for
105 the above pipe clock.
106 For "qcom,ipq8074-qmp-pcie-phy":
107 - "pcie20_phy0_pipe_clk" Pipe Clock parent
109 "pcie20_phy1_pipe_clk"
110 - #clock-cells: must be 0
111 - Phy pll outputs pipe clocks for pipe based PHYs. These clocks are then
112 gate-controlled by the gcc.
114 Required properties for child node of PHYs with lane reset, AKA:
115 "qcom,msm8996-qmp-pcie-phy"
116 - resets: a list of phandles and reset controller specifier pairs,
117 one for each entry in reset-names.
118 - reset-names: Must contain following:
119 "lane<lane-number>" for reset specific to each lane.
123 compatible = "qcom,msm8996-qmp-pcie-phy";
124 reg = <0x34000 0x488>;
125 #address-cells = <1>;
129 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
130 <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
131 <&gcc GCC_PCIE_CLKREF_CLK>;
132 clock-names = "aux", "cfg_ahb", "ref";
134 vdda-phy-supply = <&pm8994_l28>;
135 vdda-pll-supply = <&pm8994_l12>;
137 resets = <&gcc GCC_PCIE_PHY_BCR>,
138 <&gcc GCC_PCIE_PHY_COM_BCR>,
139 <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
140 reset-names = "phy", "common", "cfg";
142 pciephy_0: lane@35000 {
143 reg = <0x35000 0x130>,
149 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
150 clock-names = "pipe0";
151 clock-output-names = "pcie_0_pipe_clk_src";
152 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
153 reset-names = "lane0";
156 pciephy_1: lane@36000 {
162 compatible = "qcom,sdm845-qmp-usb3-uni-phy";
163 reg = <0x88eb000 0x18c>;
164 #address-cells = <1>;
168 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
169 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
170 <&gcc GCC_USB3_SEC_CLKREF_CLK>,
171 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
172 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
174 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
175 <&gcc GCC_USB3_PHY_SEC_BCR>;
176 reset-names = "phy", "common";
179 reg = <0x88eb200 0x128>,
185 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
186 clock-names = "pipe0";
187 clock-output-names = "usb3_uni_phy_pipe_clk_src";
192 compatible = "qcom,sdm845-qmp-ufs-phy";
193 reg = <0x1d87000 0x18c>;
194 #address-cells = <1>;
199 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
200 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
203 reg = <0x1d87400 0x108>,