1 mt65xx USB3.0 PHY binding
2 --------------------------
4 This binding describes a usb3.0 phy for mt65xx platforms of Medaitek SoC.
6 Required properties (controller (parent) node):
7 - compatible : should be one of
8 "mediatek,mt2701-u3phy"
9 "mediatek,mt2712-u3phy"
10 "mediatek,mt8173-u3phy"
11 - clocks : (deprecated, use port's clocks instead) a list of phandle +
12 clock-specifier pairs, one for each entry in clock-names
13 - clock-names : (deprecated, use port's one instead) must contain
14 "u3phya_ref": for reference clock of usb3.0 analog phy.
16 Required nodes : a sub-node is required for each port the controller
17 provides. Address range information including the usual
18 'reg' property is used inside these nodes to describe
19 the controller's topology.
21 Optional properties (controller (parent) node):
22 - reg : offset and length of register shared by multiple ports,
23 exclude port's private register. It is needed on mt2701
24 and mt8173, but not on mt2712.
26 Required properties (port (child) node):
27 - reg : address and length of the register set for the port.
28 - clocks : a list of phandle + clock-specifier pairs, one for each
30 - clock-names : must contain
31 "ref": 48M reference clock for HighSpeed analog phy; and 26M
32 reference clock for SuperSpeed analog phy, sometimes is
33 24M, 25M or 27M, depended on platform.
34 - #phy-cells : should be 1 (See second example)
35 cell after port phandle is phy type from:
41 u3phy: usb-phy@11290000 {
42 compatible = "mediatek,mt8173-u3phy";
43 reg = <0 0x11290000 0 0x800>;
49 u2port0: usb-phy@11290800 {
50 reg = <0 0x11290800 0 0x100>;
51 clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
57 u3port0: usb-phy@11290900 {
58 reg = <0 0x11290800 0 0x700>;
65 u2port1: usb-phy@11291000 {
66 reg = <0 0x11291000 0 0x100>;
67 clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>;
74 Specifying phy control of devices
75 ---------------------------------
77 Device nodes should specify the configuration required in their "phys"
78 property, containing a phandle to the phy port node and a device type;
79 phy-names for each port are optional.
83 #include <dt-bindings/phy/phy.h>
87 phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
88 phy-names = "usb2-0", "usb3-0";
93 Layout differences of banks between mt8173/mt2701 and mt2712
94 -------------------------------------------------------------
99 u2 port0 0x0800 U2PHY_COM
100 u3 port0 0x0900 U3PHYD
104 u2 port1 0x1000 U2PHY_COM
105 u3 port1 0x1100 U3PHYD
109 u2 port2 0x1800 U2PHY_COM
117 u3 port0 0x0700 SPLLC
126 u3 port1 0x1700 SPLLC
135 SPLLC shared by u3 ports and FMREG shared by u2 ports on
136 mt8173/mt2701 are put back into each port; a new bank MISC for
137 u2 ports and CHIP for u3 ports are added on mt2712.