Merge branch 'for-5.3/uclogic' into for-linus
[sfrench/cifs-2.6.git] / Documentation / devicetree / bindings / phy / nvidia,tegra124-xusb-padctl.txt
1 Device tree binding for NVIDIA Tegra XUSB pad controller
2 ========================================================
3
4 The Tegra XUSB pad controller manages a set of I/O lanes (with differential
5 signals) which connect directly to pins/pads on the SoC package. Each lane
6 is controlled by a HW block referred to as a "pad" in the Tegra hardware
7 documentation. Each such "pad" may control either one or multiple lanes,
8 and thus contains any logic common to all its lanes. Each lane can be
9 separately configured and powered up.
10
11 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
12 super-speed USB. Other lanes are for various types of low-speed, full-speed
13 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
14 contains a software-configurable mux that sits between the I/O controller
15 ports (e.g. PCIe) and the lanes.
16
17 In addition to per-lane configuration, USB 3.0 ports may require additional
18 settings on a per-board basis.
19
20 Pads will be represented as children of the top-level XUSB pad controller
21 device tree node. Each lane exposed by the pad will be represented by its
22 own subnode and can be referenced by users of the lane using the standard
23 PHY bindings, as described by the phy-bindings.txt file in this directory.
24
25 The Tegra hardware documentation refers to the connection between the XUSB
26 pad controller and the XUSB controller as "ports". This is confusing since
27 "port" is typically used to denote the physical USB receptacle. The device
28 tree binding in this document uses the term "port" to refer to the logical
29 abstraction of the signals that are routed to a USB receptacle (i.e. a PHY
30 for the USB signal, the VBUS power supply, the USB 2.0 companion port for
31 USB 3.0 receptacles, ...).
32
33 Required properties:
34 --------------------
35 - compatible: Must be:
36   - Tegra124: "nvidia,tegra124-xusb-padctl"
37   - Tegra132: "nvidia,tegra132-xusb-padctl", "nvidia,tegra124-xusb-padctl"
38   - Tegra210: "nvidia,tegra210-xusb-padctl"
39   - Tegra186: "nvidia,tegra186-xusb-padctl"
40 - reg: Physical base address and length of the controller's registers.
41 - resets: Must contain an entry for each entry in reset-names.
42 - reset-names: Must include the following entries:
43   - "padctl"
44
45 For Tegra186:
46 - avdd-pll-erefeut-supply: UPHY brick and reference clock as well as UTMI PHY
47   power supply. Must supply 1.8 V.
48 - avdd-usb-supply: USB I/Os, VBUS, ID, REXT, D+/D- power supply. Must supply
49   3.3 V.
50 - vclamp-usb-supply: Bias rail for USB pad. Must supply 1.8 V.
51 - vddio-hsic-supply: HSIC PHY power supply. Must supply 1.2 V.
52
53
54 Pad nodes:
55 ==========
56
57 A required child node named "pads" contains a list of subnodes, one for each
58 of the pads exposed by the XUSB pad controller. Each pad may need additional
59 resources that can be referenced in its pad node.
60
61 The "status" property is used to enable or disable the use of a pad. If set
62 to "disabled", the pad will not be used on the given board. In order to use
63 the pad and any of its lanes, this property must be set to "okay".
64
65 For Tegra124 and Tegra132, the following pads exist: usb2, ulpi, hsic, pcie
66 and sata. No extra resources are required for operation of these pads.
67
68 For Tegra210, the following pads exist: usb2, hsic, pcie and sata. Below is
69 a description of the properties of each pad.
70
71 UTMI pad:
72 ---------
73
74 Required properties:
75 - clocks: Must contain an entry for each entry in clock-names.
76 - clock-names: Must contain the following entries:
77   - "trk": phandle and specifier referring to the USB2 tracking clock
78
79 HSIC pad:
80 ---------
81
82 Required properties:
83 - clocks: Must contain an entry for each entry in clock-names.
84 - clock-names: Must contain the following entries:
85   - "trk": phandle and specifier referring to the HSIC tracking clock
86
87 PCIe pad:
88 ---------
89
90 Required properties:
91 - clocks: Must contain an entry for each entry in clock-names.
92 - clock-names: Must contain the following entries:
93   - "pll": phandle and specifier referring to the PLLE
94 - resets: Must contain an entry for each entry in reset-names.
95 - reset-names: Must contain the following entries:
96   - "phy": reset for the PCIe UPHY block
97
98 SATA pad:
99 ---------
100
101 Required properties:
102 - resets: Must contain an entry for each entry in reset-names.
103 - reset-names: Must contain the following entries:
104   - "phy": reset for the SATA UPHY block
105
106
107 PHY nodes:
108 ==========
109
110 Each pad node has a child named "lanes" that contains one or more children of
111 its own, each representing one of the lanes controlled by the pad.
112
113 Required properties:
114 --------------------
115 - status: Defines the operation status of the PHY. Valid values are:
116   - "disabled": the PHY is disabled
117   - "okay": the PHY is enabled
118 - #phy-cells: Should be 0. Since each lane represents a single PHY, there is
119   no need for an additional specifier.
120 - nvidia,function: The output function of the PHY. See below for a list of
121   valid functions per SoC generation.
122
123 For Tegra124 and Tegra132, the list of valid PHY nodes is given below:
124 - usb2: usb2-0, usb2-1, usb2-2
125   - functions: "snps", "xusb", "uart"
126 - ulpi: ulpi-0
127   - functions: "snps", "xusb"
128 - hsic: hsic-0, hsic-1
129   - functions: "snps", "xusb"
130 - pcie: pcie-0, pcie-1, pcie-2, pcie-3, pcie-4
131   - functions: "pcie", "usb3-ss"
132 - sata: sata-0
133   - functions: "usb3-ss", "sata"
134
135 For Tegra210, the list of valid PHY nodes is given below:
136 - usb2: usb2-0, usb2-1, usb2-2, usb2-3
137   - functions: "snps", "xusb", "uart"
138 - hsic: hsic-0, hsic-1
139   - functions: "snps", "xusb"
140 - pcie: pcie-0, pcie-1, pcie-2, pcie-3, pcie-4, pcie-5, pcie-6
141   - functions: "pcie-x1", "usb3-ss", "pcie-x4"
142 - sata: sata-0
143   - functions: "usb3-ss", "sata"
144
145
146 Port nodes:
147 ===========
148
149 A required child node named "ports" contains a list of all the ports exposed
150 by the XUSB pad controller. Per-port configuration is only required for USB.
151
152 USB2 ports:
153 -----------
154
155 Required properties:
156 - status: Defines the operation status of the port. Valid values are:
157   - "disabled": the port is disabled
158   - "okay": the port is enabled
159 - mode: A string that determines the mode in which to run the port. Valid
160   values are:
161   - "host": for USB host mode
162   - "device": for USB device mode
163   - "otg": for USB OTG mode
164
165 Optional properties:
166 - nvidia,internal: A boolean property whose presence determines that a port
167   is internal. In the absence of this property the port is considered to be
168   external.
169 - vbus-supply: phandle to a regulator supplying the VBUS voltage.
170
171 ULPI ports:
172 -----------
173
174 Optional properties:
175 - status: Defines the operation status of the port. Valid values are:
176   - "disabled": the port is disabled
177   - "okay": the port is enabled
178 - nvidia,internal: A boolean property whose presence determines that a port
179   is internal. In the absence of this property the port is considered to be
180   external.
181 - vbus-supply: phandle to a regulator supplying the VBUS voltage.
182
183 HSIC ports:
184 -----------
185
186 Required properties:
187 - status: Defines the operation status of the port. Valid values are:
188   - "disabled": the port is disabled
189   - "okay": the port is enabled
190
191 Optional properties:
192 - vbus-supply: phandle to a regulator supplying the VBUS voltage.
193
194 Super-speed USB ports:
195 ----------------------
196
197 Required properties:
198 - status: Defines the operation status of the port. Valid values are:
199   - "disabled": the port is disabled
200   - "okay": the port is enabled
201 - nvidia,usb2-companion: A single cell that specifies the physical port number
202   to map this super-speed USB port to. The range of valid port numbers varies
203   with the SoC generation:
204   - 0-2: for Tegra124 and Tegra132
205   - 0-3: for Tegra210
206
207 Optional properties:
208 - nvidia,internal: A boolean property whose presence determines that a port
209   is internal. In the absence of this property the port is considered to be
210   external.
211
212 For Tegra124 and Tegra132, the XUSB pad controller exposes the following
213 ports:
214 - 3x USB2: usb2-0, usb2-1, usb2-2
215 - 1x ULPI: ulpi-0
216 - 2x HSIC: hsic-0, hsic-1
217 - 2x super-speed USB: usb3-0, usb3-1
218
219 For Tegra210, the XUSB pad controller exposes the following ports:
220 - 4x USB2: usb2-0, usb2-1, usb2-2, usb2-3
221 - 2x HSIC: hsic-0, hsic-1
222 - 4x super-speed USB: usb3-0, usb3-1, usb3-2, usb3-3
223
224
225 Examples:
226 =========
227
228 Tegra124 and Tegra132:
229 ----------------------
230
231 SoC include:
232
233         padctl@7009f000 {
234                 /* for Tegra124 */
235                 compatible = "nvidia,tegra124-xusb-padctl";
236                 /* for Tegra132 */
237                 compatible = "nvidia,tegra132-xusb-padctl",
238                              "nvidia,tegra124-xusb-padctl";
239                 reg = <0x0 0x7009f000 0x0 0x1000>;
240                 resets = <&tegra_car 142>;
241                 reset-names = "padctl";
242
243                 pads {
244                         usb2 {
245                                 status = "disabled";
246
247                                 lanes {
248                                         usb2-0 {
249                                                 status = "disabled";
250                                                 #phy-cells = <0>;
251                                         };
252
253                                         usb2-1 {
254                                                 status = "disabled";
255                                                 #phy-cells = <0>;
256                                         };
257
258                                         usb2-2 {
259                                                 status = "disabled";
260                                                 #phy-cells = <0>;
261                                         };
262                                 };
263                         };
264
265                         ulpi {
266                                 status = "disabled";
267
268                                 lanes {
269                                         ulpi-0 {
270                                                 status = "disabled";
271                                                 #phy-cells = <0>;
272                                         };
273                                 };
274                         };
275
276                         hsic {
277                                 status = "disabled";
278
279                                 lanes {
280                                         hsic-0 {
281                                                 status = "disabled";
282                                                 #phy-cells = <0>;
283                                         };
284
285                                         hsic-1 {
286                                                 status = "disabled";
287                                                 #phy-cells = <0>;
288                                         };
289                                 };
290                         };
291
292                         pcie {
293                                 status = "disabled";
294
295                                 lanes {
296                                         pcie-0 {
297                                                 status = "disabled";
298                                                 #phy-cells = <0>;
299                                         };
300
301                                         pcie-1 {
302                                                 status = "disabled";
303                                                 #phy-cells = <0>;
304                                         };
305
306                                         pcie-2 {
307                                                 status = "disabled";
308                                                 #phy-cells = <0>;
309                                         };
310
311                                         pcie-3 {
312                                                 status = "disabled";
313                                                 #phy-cells = <0>;
314                                         };
315
316                                         pcie-4 {
317                                                 status = "disabled";
318                                                 #phy-cells = <0>;
319                                         };
320                                 };
321                         };
322
323                         sata {
324                                 status = "disabled";
325
326                                 lanes {
327                                         sata-0 {
328                                                 status = "disabled";
329                                                 #phy-cells = <0>;
330                                         };
331                                 };
332                         };
333                 };
334
335                 ports {
336                         usb2-0 {
337                                 status = "disabled";
338                         };
339
340                         usb2-1 {
341                                 status = "disabled";
342                         };
343
344                         usb2-2 {
345                                 status = "disabled";
346                         };
347
348                         ulpi-0 {
349                                 status = "disabled";
350                         };
351
352                         hsic-0 {
353                                 status = "disabled";
354                         };
355
356                         hsic-1 {
357                                 status = "disabled";
358                         };
359
360                         usb3-0 {
361                                 status = "disabled";
362                         };
363
364                         usb3-1 {
365                                 status = "disabled";
366                         };
367                 };
368         };
369
370 Board file:
371
372         padctl@7009f000 {
373                 status = "okay";
374
375                 pads {
376                         usb2 {
377                                 status = "okay";
378
379                                 lanes {
380                                         usb2-0 {
381                                                 nvidia,function = "xusb";
382                                                 status = "okay";
383                                         };
384
385                                         usb2-1 {
386                                                 nvidia,function = "xusb";
387                                                 status = "okay";
388                                         };
389
390                                         usb2-2 {
391                                                 nvidia,function = "xusb";
392                                                 status = "okay";
393                                         };
394                                 };
395                         };
396
397                         pcie {
398                                 status = "okay";
399
400                                 lanes {
401                                         pcie-0 {
402                                                 nvidia,function = "usb3-ss";
403                                                 status = "okay";
404                                         };
405
406                                         pcie-2 {
407                                                 nvidia,function = "pcie";
408                                                 status = "okay";
409                                         };
410
411                                         pcie-4 {
412                                                 nvidia,function = "pcie";
413                                                 status = "okay";
414                                         };
415                                 };
416                         };
417
418                         sata {
419                                 status = "okay";
420
421                                 lanes {
422                                         sata-0 {
423                                                 nvidia,function = "sata";
424                                                 status = "okay";
425                                         };
426                                 };
427                         };
428                 };
429
430                 ports {
431                         /* Micro A/B */
432                         usb2-0 {
433                                 status = "okay";
434                                 mode = "otg";
435                         };
436
437                         /* Mini PCIe */
438                         usb2-1 {
439                                 status = "okay";
440                                 mode = "host";
441                         };
442
443                         /* USB3 */
444                         usb2-2 {
445                                 status = "okay";
446                                 mode = "host";
447
448                                 vbus-supply = <&vdd_usb3_vbus>;
449                         };
450
451                         usb3-0 {
452                                 nvidia,port = <2>;
453                                 status = "okay";
454                         };
455                 };
456         };
457
458 Tegra210:
459 ---------
460
461 SoC include:
462
463         padctl@7009f000 {
464                 compatible = "nvidia,tegra210-xusb-padctl";
465                 reg = <0x0 0x7009f000 0x0 0x1000>;
466                 resets = <&tegra_car 142>;
467                 reset-names = "padctl";
468
469                 status = "disabled";
470
471                 pads {
472                         usb2 {
473                                 clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>;
474                                 clock-names = "trk";
475                                 status = "disabled";
476
477                                 lanes {
478                                         usb2-0 {
479                                                 status = "disabled";
480                                                 #phy-cells = <0>;
481                                         };
482
483                                         usb2-1 {
484                                                 status = "disabled";
485                                                 #phy-cells = <0>;
486                                         };
487
488                                         usb2-2 {
489                                                 status = "disabled";
490                                                 #phy-cells = <0>;
491                                         };
492
493                                         usb2-3 {
494                                                 status = "disabled";
495                                                 #phy-cells = <0>;
496                                         };
497                                 };
498                         };
499
500                         hsic {
501                                 clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>;
502                                 clock-names = "trk";
503                                 status = "disabled";
504
505                                 lanes {
506                                         hsic-0 {
507                                                 status = "disabled";
508                                                 #phy-cells = <0>;
509                                         };
510
511                                         hsic-1 {
512                                                 status = "disabled";
513                                                 #phy-cells = <0>;
514                                         };
515                                 };
516                         };
517
518                         pcie {
519                                 clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
520                                 clock-names = "pll";
521                                 resets = <&tegra_car 205>;
522                                 reset-names = "phy";
523                                 status = "disabled";
524
525                                 lanes {
526                                         pcie-0 {
527                                                 status = "disabled";
528                                                 #phy-cells = <0>;
529                                         };
530
531                                         pcie-1 {
532                                                 status = "disabled";
533                                                 #phy-cells = <0>;
534                                         };
535
536                                         pcie-2 {
537                                                 status = "disabled";
538                                                 #phy-cells = <0>;
539                                         };
540
541                                         pcie-3 {
542                                                 status = "disabled";
543                                                 #phy-cells = <0>;
544                                         };
545
546                                         pcie-4 {
547                                                 status = "disabled";
548                                                 #phy-cells = <0>;
549                                         };
550
551                                         pcie-5 {
552                                                 status = "disabled";
553                                                 #phy-cells = <0>;
554                                         };
555
556                                         pcie-6 {
557                                                 status = "disabled";
558                                                 #phy-cells = <0>;
559                                         };
560                                 };
561                         };
562
563                         sata {
564                                 clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
565                                 clock-names = "pll";
566                                 resets = <&tegra_car 204>;
567                                 reset-names = "phy";
568                                 status = "disabled";
569
570                                 lanes {
571                                         sata-0 {
572                                                 status = "disabled";
573                                                 #phy-cells = <0>;
574                                         };
575                                 };
576                         };
577                 };
578
579                 ports {
580                         usb2-0 {
581                                 status = "disabled";
582                         };
583
584                         usb2-1 {
585                                 status = "disabled";
586                         };
587
588                         usb2-2 {
589                                 status = "disabled";
590                         };
591
592                         usb2-3 {
593                                 status = "disabled";
594                         };
595
596                         hsic-0 {
597                                 status = "disabled";
598                         };
599
600                         hsic-1 {
601                                 status = "disabled";
602                         };
603
604                         usb3-0 {
605                                 status = "disabled";
606                         };
607
608                         usb3-1 {
609                                 status = "disabled";
610                         };
611
612                         usb3-2 {
613                                 status = "disabled";
614                         };
615
616                         usb3-3 {
617                                 status = "disabled";
618                         };
619                 };
620         };
621
622 Board file:
623
624         padctl@7009f000 {
625                 status = "okay";
626
627                 pads {
628                         usb2 {
629                                 status = "okay";
630
631                                 lanes {
632                                         usb2-0 {
633                                                 nvidia,function = "xusb";
634                                                 status = "okay";
635                                         };
636
637                                         usb2-1 {
638                                                 nvidia,function = "xusb";
639                                                 status = "okay";
640                                         };
641
642                                         usb2-2 {
643                                                 nvidia,function = "xusb";
644                                                 status = "okay";
645                                         };
646
647                                         usb2-3 {
648                                                 nvidia,function = "xusb";
649                                                 status = "okay";
650                                         };
651                                 };
652                         };
653
654                         pcie {
655                                 status = "okay";
656
657                                 lanes {
658                                         pcie-0 {
659                                                 nvidia,function = "pcie-x1";
660                                                 status = "okay";
661                                         };
662
663                                         pcie-1 {
664                                                 nvidia,function = "pcie-x4";
665                                                 status = "okay";
666                                         };
667
668                                         pcie-2 {
669                                                 nvidia,function = "pcie-x4";
670                                                 status = "okay";
671                                         };
672
673                                         pcie-3 {
674                                                 nvidia,function = "pcie-x4";
675                                                 status = "okay";
676                                         };
677
678                                         pcie-4 {
679                                                 nvidia,function = "pcie-x4";
680                                                 status = "okay";
681                                         };
682
683                                         pcie-5 {
684                                                 nvidia,function = "usb3-ss";
685                                                 status = "okay";
686                                         };
687
688                                         pcie-6 {
689                                                 nvidia,function = "usb3-ss";
690                                                 status = "okay";
691                                         };
692                                 };
693                         };
694
695                         sata {
696                                 status = "okay";
697
698                                 lanes {
699                                         sata-0 {
700                                                 nvidia,function = "sata";
701                                                 status = "okay";
702                                         };
703                                 };
704                         };
705                 };
706
707                 ports {
708                         usb2-0 {
709                                 status = "okay";
710                                 mode = "otg";
711                         };
712
713                         usb2-1 {
714                                 status = "okay";
715                                 vbus-supply = <&vdd_5v0_rtl>;
716                                 mode = "host";
717                         };
718
719                         usb2-2 {
720                                 status = "okay";
721                                 vbus-supply = <&vdd_usb_vbus>;
722                                 mode = "host";
723                         };
724
725                         usb2-3 {
726                                 status = "okay";
727                                 mode = "host";
728                         };
729
730                         usb3-0 {
731                                 status = "okay";
732                                 nvidia,lanes = "pcie-6";
733                                 nvidia,port = <1>;
734                         };
735
736                         usb3-1 {
737                                 status = "okay";
738                                 nvidia,lanes = "pcie-5";
739                                 nvidia,port = <2>;
740                         };
741                 };
742         };