Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt

   1 Device tree binding for NVIDIA Tegra XUSB pad controller
   2 ========================================================
   3
   4 The Tegra XUSB pad controller manages a set of I/O lanes (with differential
   5 signals) which connect directly to pins/pads on the SoC package. Each lane
   6 is controlled by a HW block referred to as a "pad" in the Tegra hardware
   7 documentation. Each such "pad" may control either one or multiple lanes,
   8 and thus contains any logic common to all its lanes. Each lane can be
   9 separately configured and powered up.
  10
  11 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
  12 super-speed USB. Other lanes are for various types of low-speed, full-speed
  13 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
  14 contains a software-configurable mux that sits between the I/O controller
  15 ports (e.g. PCIe) and the lanes.
  16
  17 In addition to per-lane configuration, USB 3.0 ports may require additional
  18 settings on a per-board basis.
  19
  20 Pads will be represented as children of the top-level XUSB pad controller
  21 device tree node. Each lane exposed by the pad will be represented by its
  22 own subnode and can be referenced by users of the lane using the standard
  23 PHY bindings, as described by the phy-bindings.txt file in this directory.
  24
  25 The Tegra hardware documentation refers to the connection between the XUSB
  26 pad controller and the XUSB controller as "ports". This is confusing since
  27 "port" is typically used to denote the physical USB receptacle. The device
  28 tree binding in this document uses the term "port" to refer to the logical
  29 abstraction of the signals that are routed to a USB receptacle (i.e. a PHY
  30 for the USB signal, the VBUS power supply, the USB 2.0 companion port for
  31 USB 3.0 receptacles, ...).
  32
  33 Required properties:
  34 --------------------
  35 - compatible: Must be:
  36   - Tegra124: "nvidia,tegra124-xusb-padctl"
  37   - Tegra132: "nvidia,tegra132-xusb-padctl", "nvidia,tegra124-xusb-padctl"
  38   - Tegra210: "nvidia,tegra210-xusb-padctl"
  39 - reg: Physical base address and length of the controller's registers.
  40 - resets: Must contain an entry for each entry in reset-names.
  41 - reset-names: Must include the following entries:
  42   - "padctl"
  43
  44
  45 Pad nodes:
  46 ==========
  47
  48 A required child node named "pads" contains a list of subnodes, one for each
  49 of the pads exposed by the XUSB pad controller. Each pad may need additional
  50 resources that can be referenced in its pad node.
  51
  52 The "status" property is used to enable or disable the use of a pad. If set
  53 to "disabled", the pad will not be used on the given board. In order to use
  54 the pad and any of its lanes, this property must be set to "okay".
  55
  56 For Tegra124 and Tegra132, the following pads exist: usb2, ulpi, hsic, pcie
  57 and sata. No extra resources are required for operation of these pads.
  58
  59 For Tegra210, the following pads exist: usb2, hsic, pcie and sata. Below is
  60 a description of the properties of each pad.
  61
  62 UTMI pad:
  63 ---------
  64
  65 Required properties:
  66 - clocks: Must contain an entry for each entry in clock-names.
  67 - clock-names: Must contain the following entries:
  68   - "trk": phandle and specifier referring to the USB2 tracking clock
  69
  70 HSIC pad:
  71 ---------
  72
  73 Required properties:
  74 - clocks: Must contain an entry for each entry in clock-names.
  75 - clock-names: Must contain the following entries:
  76   - "trk": phandle and specifier referring to the HSIC tracking clock
  77
  78 PCIe pad:
  79 ---------
  80
  81 Required properties:
  82 - clocks: Must contain an entry for each entry in clock-names.
  83 - clock-names: Must contain the following entries:
  84   - "pll": phandle and specifier referring to the PLLE
  85 - resets: Must contain an entry for each entry in reset-names.
  86 - reset-names: Must contain the following entries:
  87   - "phy": reset for the PCIe UPHY block
  88
  89 SATA pad:
  90 ---------
  91
  92 Required properties:
  93 - resets: Must contain an entry for each entry in reset-names.
  94 - reset-names: Must contain the following entries:
  95   - "phy": reset for the SATA UPHY block
  96
  97
  98 PHY nodes:
  99 ==========
 100
 101 Each pad node has a child named "lanes" that contains one or more children of
 102 its own, each representing one of the lanes controlled by the pad.
 103
 104 Required properties:
 105 --------------------
 106 - status: Defines the operation status of the PHY. Valid values are:
 107   - "disabled": the PHY is disabled
 108   - "okay": the PHY is enabled
 109 - #phy-cells: Should be 0. Since each lane represents a single PHY, there is
 110   no need for an additional specifier.
 111 - nvidia,function: The output function of the PHY. See below for a list of
 112   valid functions per SoC generation.
 113
 114 For Tegra124 and Tegra132, the list of valid PHY nodes is given below:
 115 - usb2: usb2-0, usb2-1, usb2-2
 116   - functions: "snps", "xusb", "uart"
 117 - ulpi: ulpi-0
 118   - functions: "snps", "xusb"
 119 - hsic: hsic-0, hsic-1
 120   - functions: "snps", "xusb"
 121 - pcie: pcie-0, pcie-1, pcie-2, pcie-3, pcie-4
 122   - functions: "pcie", "usb3-ss"
 123 - sata: sata-0
 124   - functions: "usb3-ss", "sata"
 125
 126 For Tegra210, the list of valid PHY nodes is given below:
 127 - usb2: usb2-0, usb2-1, usb2-2, usb2-3
 128   - functions: "snps", "xusb", "uart"
 129 - hsic: hsic-0, hsic-1
 130   - functions: "snps", "xusb"
 131 - pcie: pcie-0, pcie-1, pcie-2, pcie-3, pcie-4, pcie-5, pcie-6
 132   - functions: "pcie-x1", "usb3-ss", "pcie-x4"
 133 - sata: sata-0
 134   - functions: "usb3-ss", "sata"
 135
 136
 137 Port nodes:
 138 ===========
 139
 140 A required child node named "ports" contains a list of all the ports exposed
 141 by the XUSB pad controller. Per-port configuration is only required for USB.
 142
 143 USB2 ports:
 144 -----------
 145
 146 Required properties:
 147 - status: Defines the operation status of the port. Valid values are:
 148   - "disabled": the port is disabled
 149   - "okay": the port is enabled
 150 - mode: A string that determines the mode in which to run the port. Valid
 151   values are:
 152   - "host": for USB host mode
 153   - "device": for USB device mode
 154   - "otg": for USB OTG mode
 155
 156 Optional properties:
 157 - nvidia,internal: A boolean property whose presence determines that a port
 158   is internal. In the absence of this property the port is considered to be
 159   external.
 160 - vbus-supply: phandle to a regulator supplying the VBUS voltage.
 161
 162 ULPI ports:
 163 -----------
 164
 165 Optional properties:
 166 - status: Defines the operation status of the port. Valid values are:
 167   - "disabled": the port is disabled
 168   - "okay": the port is enabled
 169 - nvidia,internal: A boolean property whose presence determines that a port
 170   is internal. In the absence of this property the port is considered to be
 171   external.
 172 - vbus-supply: phandle to a regulator supplying the VBUS voltage.
 173
 174 HSIC ports:
 175 -----------
 176
 177 Required properties:
 178 - status: Defines the operation status of the port. Valid values are:
 179   - "disabled": the port is disabled
 180   - "okay": the port is enabled
 181
 182 Optional properties:
 183 - vbus-supply: phandle to a regulator supplying the VBUS voltage.
 184
 185 Super-speed USB ports:
 186 ----------------------
 187
 188 Required properties:
 189 - status: Defines the operation status of the port. Valid values are:
 190   - "disabled": the port is disabled
 191   - "okay": the port is enabled
 192 - nvidia,usb2-companion: A single cell that specifies the physical port number
 193   to map this super-speed USB port to. The range of valid port numbers varies
 194   with the SoC generation:
 195   - 0-2: for Tegra124 and Tegra132
 196   - 0-3: for Tegra210
 197
 198 Optional properties:
 199 - nvidia,internal: A boolean property whose presence determines that a port
 200   is internal. In the absence of this property the port is considered to be
 201   external.
 202
 203 For Tegra124 and Tegra132, the XUSB pad controller exposes the following
 204 ports:
 205 - 3x USB2: usb2-0, usb2-1, usb2-2
 206 - 1x ULPI: ulpi-0
 207 - 2x HSIC: hsic-0, hsic-1
 208 - 2x super-speed USB: usb3-0, usb3-1
 209
 210 For Tegra210, the XUSB pad controller exposes the following ports:
 211 - 4x USB2: usb2-0, usb2-1, usb2-2, usb2-3
 212 - 2x HSIC: hsic-0, hsic-1
 213 - 4x super-speed USB: usb3-0, usb3-1, usb3-2, usb3-3
 214
 215
 216 Examples:
 217 =========
 218
 219 Tegra124 and Tegra132:
 220 ----------------------
 221
 222 SoC include:
 223
 224         padctl@7009f000 {
 225                 /* for Tegra124 */
 226                 compatible = "nvidia,tegra124-xusb-padctl";
 227                 /* for Tegra132 */
 228                 compatible = "nvidia,tegra132-xusb-padctl",
 229                              "nvidia,tegra124-xusb-padctl";
 230                 reg = <0x0 0x7009f000 0x0 0x1000>;
 231                 resets = <&tegra_car 142>;
 232                 reset-names = "padctl";
 233
 234                 pads {
 235                         usb2 {
 236                                 status = "disabled";
 237
 238                                 lanes {
 239                                         usb2-0 {
 240                                                 status = "disabled";
 241                                                 #phy-cells = <0>;
 242                                         };
 243
 244                                         usb2-1 {
 245                                                 status = "disabled";
 246                                                 #phy-cells = <0>;
 247                                         };
 248
 249                                         usb2-2 {
 250                                                 status = "disabled";
 251                                                 #phy-cells = <0>;
 252                                         };
 253                                 };
 254                         };
 255
 256                         ulpi {
 257                                 status = "disabled";
 258
 259                                 lanes {
 260                                         ulpi-0 {
 261                                                 status = "disabled";
 262                                                 #phy-cells = <0>;
 263                                         };
 264                                 };
 265                         };
 266
 267                         hsic {
 268                                 status = "disabled";
 269
 270                                 lanes {
 271                                         hsic-0 {
 272                                                 status = "disabled";
 273                                                 #phy-cells = <0>;
 274                                         };
 275
 276                                         hsic-1 {
 277                                                 status = "disabled";
 278                                                 #phy-cells = <0>;
 279                                         };
 280                                 };
 281                         };
 282
 283                         pcie {
 284                                 status = "disabled";
 285
 286                                 lanes {
 287                                         pcie-0 {
 288                                                 status = "disabled";
 289                                                 #phy-cells = <0>;
 290                                         };
 291
 292                                         pcie-1 {
 293                                                 status = "disabled";
 294                                                 #phy-cells = <0>;
 295                                         };
 296
 297                                         pcie-2 {
 298                                                 status = "disabled";
 299                                                 #phy-cells = <0>;
 300                                         };
 301
 302                                         pcie-3 {
 303                                                 status = "disabled";
 304                                                 #phy-cells = <0>;
 305                                         };
 306
 307                                         pcie-4 {
 308                                                 status = "disabled";
 309                                                 #phy-cells = <0>;
 310                                         };
 311                                 };
 312                         };
 313
 314                         sata {
 315                                 status = "disabled";
 316
 317                                 lanes {
 318                                         sata-0 {
 319                                                 status = "disabled";
 320                                                 #phy-cells = <0>;
 321                                         };
 322                                 };
 323                         };
 324                 };
 325
 326                 ports {
 327                         usb2-0 {
 328                                 status = "disabled";
 329                         };
 330
 331                         usb2-1 {
 332                                 status = "disabled";
 333                         };
 334
 335                         usb2-2 {
 336                                 status = "disabled";
 337                         };
 338
 339                         ulpi-0 {
 340                                 status = "disabled";
 341                         };
 342
 343                         hsic-0 {
 344                                 status = "disabled";
 345                         };
 346
 347                         hsic-1 {
 348                                 status = "disabled";
 349                         };
 350
 351                         usb3-0 {
 352                                 status = "disabled";
 353                         };
 354
 355                         usb3-1 {
 356                                 status = "disabled";
 357                         };
 358                 };
 359         };
 360
 361 Board file:
 362
 363         padctl@7009f000 {
 364                 status = "okay";
 365
 366                 pads {
 367                         usb2 {
 368                                 status = "okay";
 369
 370                                 lanes {
 371                                         usb2-0 {
 372                                                 nvidia,function = "xusb";
 373                                                 status = "okay";
 374                                         };
 375
 376                                         usb2-1 {
 377                                                 nvidia,function = "xusb";
 378                                                 status = "okay";
 379                                         };
 380
 381                                         usb2-2 {
 382                                                 nvidia,function = "xusb";
 383                                                 status = "okay";
 384                                         };
 385                                 };
 386                         };
 387
 388                         pcie {
 389                                 status = "okay";
 390
 391                                 lanes {
 392                                         pcie-0 {
 393                                                 nvidia,function = "usb3-ss";
 394                                                 status = "okay";
 395                                         };
 396
 397                                         pcie-2 {
 398                                                 nvidia,function = "pcie";
 399                                                 status = "okay";
 400                                         };
 401
 402                                         pcie-4 {
 403                                                 nvidia,function = "pcie";
 404                                                 status = "okay";
 405                                         };
 406                                 };
 407                         };
 408
 409                         sata {
 410                                 status = "okay";
 411
 412                                 lanes {
 413                                         sata-0 {
 414                                                 nvidia,function = "sata";
 415                                                 status = "okay";
 416                                         };
 417                                 };
 418                         };
 419                 };
 420
 421                 ports {
 422                         /* Micro A/B */
 423                         usb2-0 {
 424                                 status = "okay";
 425                                 mode = "otg";
 426                         };
 427
 428                         /* Mini PCIe */
 429                         usb2-1 {
 430                                 status = "okay";
 431                                 mode = "host";
 432                         };
 433
 434                         /* USB3 */
 435                         usb2-2 {
 436                                 status = "okay";
 437                                 mode = "host";
 438
 439                                 vbus-supply = <&vdd_usb3_vbus>;
 440                         };
 441
 442                         usb3-0 {
 443                                 nvidia,port = <2>;
 444                                 status = "okay";
 445                         };
 446                 };
 447         };
 448
 449 Tegra210:
 450 ---------
 451
 452 SoC include:
 453
 454         padctl@7009f000 {
 455                 compatible = "nvidia,tegra210-xusb-padctl";
 456                 reg = <0x0 0x7009f000 0x0 0x1000>;
 457                 resets = <&tegra_car 142>;
 458                 reset-names = "padctl";
 459
 460                 status = "disabled";
 461
 462                 pads {
 463                         usb2 {
 464                                 clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>;
 465                                 clock-names = "trk";
 466                                 status = "disabled";
 467
 468                                 lanes {
 469                                         usb2-0 {
 470                                                 status = "disabled";
 471                                                 #phy-cells = <0>;
 472                                         };
 473
 474                                         usb2-1 {
 475                                                 status = "disabled";
 476                                                 #phy-cells = <0>;
 477                                         };
 478
 479                                         usb2-2 {
 480                                                 status = "disabled";
 481                                                 #phy-cells = <0>;
 482                                         };
 483
 484                                         usb2-3 {
 485                                                 status = "disabled";
 486                                                 #phy-cells = <0>;
 487                                         };
 488                                 };
 489                         };
 490
 491                         hsic {
 492                                 clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>;
 493                                 clock-names = "trk";
 494                                 status = "disabled";
 495
 496                                 lanes {
 497                                         hsic-0 {
 498                                                 status = "disabled";
 499                                                 #phy-cells = <0>;
 500                                         };
 501
 502                                         hsic-1 {
 503                                                 status = "disabled";
 504                                                 #phy-cells = <0>;
 505                                         };
 506                                 };
 507                         };
 508
 509                         pcie {
 510                                 clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
 511                                 clock-names = "pll";
 512                                 resets = <&tegra_car 205>;
 513                                 reset-names = "phy";
 514                                 status = "disabled";
 515
 516                                 lanes {
 517                                         pcie-0 {
 518                                                 status = "disabled";
 519                                                 #phy-cells = <0>;
 520                                         };
 521
 522                                         pcie-1 {
 523                                                 status = "disabled";
 524                                                 #phy-cells = <0>;
 525                                         };
 526
 527                                         pcie-2 {
 528                                                 status = "disabled";
 529                                                 #phy-cells = <0>;
 530                                         };
 531
 532                                         pcie-3 {
 533                                                 status = "disabled";
 534                                                 #phy-cells = <0>;
 535                                         };
 536
 537                                         pcie-4 {
 538                                                 status = "disabled";
 539                                                 #phy-cells = <0>;
 540                                         };
 541
 542                                         pcie-5 {
 543                                                 status = "disabled";
 544                                                 #phy-cells = <0>;
 545                                         };
 546
 547                                         pcie-6 {
 548                                                 status = "disabled";
 549                                                 #phy-cells = <0>;
 550                                         };
 551                                 };
 552                         };
 553
 554                         sata {
 555                                 clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
 556                                 clock-names = "pll";
 557                                 resets = <&tegra_car 204>;
 558                                 reset-names = "phy";
 559                                 status = "disabled";
 560
 561                                 lanes {
 562                                         sata-0 {
 563                                                 status = "disabled";
 564                                                 #phy-cells = <0>;
 565                                         };
 566                                 };
 567                         };
 568                 };
 569
 570                 ports {
 571                         usb2-0 {
 572                                 status = "disabled";
 573                         };
 574
 575                         usb2-1 {
 576                                 status = "disabled";
 577                         };
 578
 579                         usb2-2 {
 580                                 status = "disabled";
 581                         };
 582
 583                         usb2-3 {
 584                                 status = "disabled";
 585                         };
 586
 587                         hsic-0 {
 588                                 status = "disabled";
 589                         };
 590
 591                         hsic-1 {
 592                                 status = "disabled";
 593                         };
 594
 595                         usb3-0 {
 596                                 status = "disabled";
 597                         };
 598
 599                         usb3-1 {
 600                                 status = "disabled";
 601                         };
 602
 603                         usb3-2 {
 604                                 status = "disabled";
 605                         };
 606
 607                         usb3-3 {
 608                                 status = "disabled";
 609                         };
 610                 };
 611         };
 612
 613 Board file:
 614
 615         padctl@7009f000 {
 616                 status = "okay";
 617
 618                 pads {
 619                         usb2 {
 620                                 status = "okay";
 621
 622                                 lanes {
 623                                         usb2-0 {
 624                                                 nvidia,function = "xusb";
 625                                                 status = "okay";
 626                                         };
 627
 628                                         usb2-1 {
 629                                                 nvidia,function = "xusb";
 630                                                 status = "okay";
 631                                         };
 632
 633                                         usb2-2 {
 634                                                 nvidia,function = "xusb";
 635                                                 status = "okay";
 636                                         };
 637
 638                                         usb2-3 {
 639                                                 nvidia,function = "xusb";
 640                                                 status = "okay";
 641                                         };
 642                                 };
 643                         };
 644
 645                         pcie {
 646                                 status = "okay";
 647
 648                                 lanes {
 649                                         pcie-0 {
 650                                                 nvidia,function = "pcie-x1";
 651                                                 status = "okay";
 652                                         };
 653
 654                                         pcie-1 {
 655                                                 nvidia,function = "pcie-x4";
 656                                                 status = "okay";
 657                                         };
 658
 659                                         pcie-2 {
 660                                                 nvidia,function = "pcie-x4";
 661                                                 status = "okay";
 662                                         };
 663
 664                                         pcie-3 {
 665                                                 nvidia,function = "pcie-x4";
 666                                                 status = "okay";
 667                                         };
 668
 669                                         pcie-4 {
 670                                                 nvidia,function = "pcie-x4";
 671                                                 status = "okay";
 672                                         };
 673
 674                                         pcie-5 {
 675                                                 nvidia,function = "usb3-ss";
 676                                                 status = "okay";
 677                                         };
 678
 679                                         pcie-6 {
 680                                                 nvidia,function = "usb3-ss";
 681                                                 status = "okay";
 682                                         };
 683                                 };
 684                         };
 685
 686                         sata {
 687                                 status = "okay";
 688
 689                                 lanes {
 690                                         sata-0 {
 691                                                 nvidia,function = "sata";
 692                                                 status = "okay";
 693                                         };
 694                                 };
 695                         };
 696                 };
 697
 698                 ports {
 699                         usb2-0 {
 700                                 status = "okay";
 701                                 mode = "otg";
 702                         };
 703
 704                         usb2-1 {
 705                                 status = "okay";
 706                                 vbus-supply = <&vdd_5v0_rtl>;
 707                                 mode = "host";
 708                         };
 709
 710                         usb2-2 {
 711                                 status = "okay";
 712                                 vbus-supply = <&vdd_usb_vbus>;
 713                                 mode = "host";
 714                         };
 715
 716                         usb2-3 {
 717                                 status = "okay";
 718                                 mode = "host";
 719                         };
 720
 721                         usb3-0 {
 722                                 status = "okay";
 723                                 nvidia,lanes = "pcie-6";
 724                                 nvidia,port = <1>;
 725                         };
 726
 727                         usb3-1 {
 728                                 status = "okay";
 729                                 nvidia,lanes = "pcie-5";
 730                                 nvidia,port = <2>;
 731                         };
 732                 };
 733         };