Documentation/devicetree/bindings/pci/qcom,pcie.txt

   1 * Qualcomm PCI express root complex
   2
   3 - compatible:
   4         Usage: required
   5         Value type: <stringlist>
   6         Definition: Value should contain
   7                         - "qcom,pcie-ipq8064" for ipq8064
   8                         - "qcom,pcie-apq8064" for apq8064
   9                         - "qcom,pcie-apq8084" for apq8084
  10                         - "qcom,pcie-msm8996" for msm8996 or apq8096
  11                         - "qcom,pcie-ipq4019" for ipq4019
  12                         - "qcom,pcie-ipq8074" for ipq8074
  13                         - "qcom,pcie-qcs404" for qcs404
  14
  15 - reg:
  16         Usage: required
  17         Value type: <prop-encoded-array>
  18         Definition: Register ranges as listed in the reg-names property
  19
  20 - reg-names:
  21         Usage: required
  22         Value type: <stringlist>
  23         Definition: Must include the following entries
  24                         - "parf"   Qualcomm specific registers
  25                         - "dbi"    DesignWare PCIe registers
  26                         - "elbi"   External local bus interface registers
  27                         - "config" PCIe configuration space
  28
  29 - device_type:
  30         Usage: required
  31         Value type: <string>
  32         Definition: Should be "pci". As specified in designware-pcie.txt
  33
  34 - #address-cells:
  35         Usage: required
  36         Value type: <u32>
  37         Definition: Should be 3. As specified in designware-pcie.txt
  38
  39 - #size-cells:
  40         Usage: required
  41         Value type: <u32>
  42         Definition: Should be 2. As specified in designware-pcie.txt
  43
  44 - ranges:
  45         Usage: required
  46         Value type: <prop-encoded-array>
  47         Definition: As specified in designware-pcie.txt
  48
  49 - interrupts:
  50         Usage: required
  51         Value type: <prop-encoded-array>
  52         Definition: MSI interrupt
  53
  54 - interrupt-names:
  55         Usage: required
  56         Value type: <stringlist>
  57         Definition: Should contain "msi"
  58
  59 - #interrupt-cells:
  60         Usage: required
  61         Value type: <u32>
  62         Definition: Should be 1. As specified in designware-pcie.txt
  63
  64 - interrupt-map-mask:
  65         Usage: required
  66         Value type: <prop-encoded-array>
  67         Definition: As specified in designware-pcie.txt
  68
  69 - interrupt-map:
  70         Usage: required
  71         Value type: <prop-encoded-array>
  72         Definition: As specified in designware-pcie.txt
  73
  74 - clocks:
  75         Usage: required
  76         Value type: <prop-encoded-array>
  77         Definition: List of phandle and clock specifier pairs as listed
  78                     in clock-names property
  79
  80 - clock-names:
  81         Usage: required
  82         Value type: <stringlist>
  83         Definition: Should contain the following entries
  84                         - "iface"       Configuration AHB clock
  85
  86 - clock-names:
  87         Usage: required for ipq/apq8064
  88         Value type: <stringlist>
  89         Definition: Should contain the following entries
  90                         - "core"        Clocks the pcie hw block
  91                         - "phy"         Clocks the pcie PHY block
  92 - clock-names:
  93         Usage: required for apq8084/ipq4019
  94         Value type: <stringlist>
  95         Definition: Should contain the following entries
  96                         - "aux"         Auxiliary (AUX) clock
  97                         - "bus_master"  Master AXI clock
  98                         - "bus_slave"   Slave AXI clock
  99
 100 - clock-names:
 101         Usage: required for msm8996/apq8096
 102         Value type: <stringlist>
 103         Definition: Should contain the following entries
 104                         - "pipe"        Pipe Clock driving internal logic
 105                         - "aux"         Auxiliary (AUX) clock
 106                         - "cfg"         Configuration clock
 107                         - "bus_master"  Master AXI clock
 108                         - "bus_slave"   Slave AXI clock
 109
 110 - clock-names:
 111         Usage: required for ipq8074
 112         Value type: <stringlist>
 113         Definition: Should contain the following entries
 114                         - "iface"       PCIe to SysNOC BIU clock
 115                         - "axi_m"       AXI Master clock
 116                         - "axi_s"       AXI Slave clock
 117                         - "ahb"         AHB clock
 118                         - "aux"         Auxiliary clock
 119
 120 - clock-names:
 121         Usage: required for qcs404
 122         Value type: <stringlist>
 123         Definition: Should contain the following entries
 124                         - "iface"       AHB clock
 125                         - "aux"         Auxiliary clock
 126                         - "master_bus"  AXI Master clock
 127                         - "slave_bus"   AXI Slave clock
 128
 129 - resets:
 130         Usage: required
 131         Value type: <prop-encoded-array>
 132         Definition: List of phandle and reset specifier pairs as listed
 133                     in reset-names property
 134
 135 - reset-names:
 136         Usage: required for ipq/apq8064
 137         Value type: <stringlist>
 138         Definition: Should contain the following entries
 139                         - "axi"  AXI reset
 140                         - "ahb"  AHB reset
 141                         - "por"  POR reset
 142                         - "pci"  PCI reset
 143                         - "phy"  PHY reset
 144
 145 - reset-names:
 146         Usage: required for apq8084
 147         Value type: <stringlist>
 148         Definition: Should contain the following entries
 149                         - "core" Core reset
 150
 151 - reset-names:
 152         Usage: required for ipq/apq8064
 153         Value type: <stringlist>
 154         Definition: Should contain the following entries
 155                         - "axi_m"               AXI master reset
 156                         - "axi_s"               AXI slave reset
 157                         - "pipe"                PIPE reset
 158                         - "axi_m_vmid"          VMID reset
 159                         - "axi_s_xpu"           XPU reset
 160                         - "parf"                PARF reset
 161                         - "phy"                 PHY reset
 162                         - "axi_m_sticky"        AXI sticky reset
 163                         - "pipe_sticky"         PIPE sticky reset
 164                         - "pwr"                 PWR reset
 165                         - "ahb"                 AHB reset
 166                         - "phy_ahb"             PHY AHB reset
 167
 168 - reset-names:
 169         Usage: required for ipq8074
 170         Value type: <stringlist>
 171         Definition: Should contain the following entries
 172                         - "pipe"                PIPE reset
 173                         - "sleep"               Sleep reset
 174                         - "sticky"              Core Sticky reset
 175                         - "axi_m"               AXI Master reset
 176                         - "axi_s"               AXI Slave reset
 177                         - "ahb"                 AHB Reset
 178                         - "axi_m_sticky"        AXI Master Sticky reset
 179
 180 - reset-names:
 181         Usage: required for qcs404
 182         Value type: <stringlist>
 183         Definition: Should contain the following entries
 184                         - "axi_m"               AXI Master reset
 185                         - "axi_s"               AXI Slave reset
 186                         - "axi_m_sticky"        AXI Master Sticky reset
 187                         - "pipe_sticky"         PIPE sticky reset
 188                         - "pwr"                 PWR reset
 189                         - "ahb"                 AHB reset
 190
 191 - power-domains:
 192         Usage: required for apq8084 and msm8996/apq8096
 193         Value type: <prop-encoded-array>
 194         Definition: A phandle and power domain specifier pair to the
 195                     power domain which is responsible for collapsing
 196                     and restoring power to the peripheral
 197
 198 - vdda-supply:
 199         Usage: required
 200         Value type: <phandle>
 201         Definition: A phandle to the core analog power supply
 202
 203 - vdda_phy-supply:
 204         Usage: required for ipq/apq8064
 205         Value type: <phandle>
 206         Definition: A phandle to the analog power supply for PHY
 207
 208 - vdda_refclk-supply:
 209         Usage: required for ipq/apq8064
 210         Value type: <phandle>
 211         Definition: A phandle to the analog power supply for IC which generates
 212                     reference clock
 213 - vddpe-3v3-supply:
 214         Usage: optional
 215         Value type: <phandle>
 216         Definition: A phandle to the PCIe endpoint power supply
 217
 218 - phys:
 219         Usage: required for apq8084 and qcs404
 220         Value type: <phandle>
 221         Definition: List of phandle(s) as listed in phy-names property
 222
 223 - phy-names:
 224         Usage: required for apq8084 and qcs404
 225         Value type: <stringlist>
 226         Definition: Should contain "pciephy"
 227
 228 - <name>-gpios:
 229         Usage: optional
 230         Value type: <prop-encoded-array>
 231         Definition: List of phandle and GPIO specifier pairs. Should contain
 232                         - "perst-gpios" PCIe endpoint reset signal line
 233                         - "wake-gpios"  PCIe endpoint wake signal line
 234
 235 * Example for ipq/apq8064
 236         pcie@1b500000 {
 237                 compatible = "qcom,pcie-apq8064", "qcom,pcie-ipq8064", "snps,dw-pcie";
 238                 reg = <0x1b500000 0x1000
 239                        0x1b502000 0x80
 240                        0x1b600000 0x100
 241                        0x0ff00000 0x100000>;
 242                 reg-names = "dbi", "elbi", "parf", "config";
 243                 device_type = "pci";
 244                 linux,pci-domain = <0>;
 245                 bus-range = <0x00 0xff>;
 246                 num-lanes = <1>;
 247                 #address-cells = <3>;
 248                 #size-cells = <2>;
 249                 ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000   /* I/O */
 250                           0x82000000 0 0 0x08000000 0 0x07e00000>; /* memory */
 251                 interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>;
 252                 interrupt-names = "msi";
 253                 #interrupt-cells = <1>;
 254                 interrupt-map-mask = <0 0 0 0x7>;
 255                 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 256                                 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 257                                 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 258                                 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 259                 clocks = <&gcc PCIE_A_CLK>,
 260                          <&gcc PCIE_H_CLK>,
 261                          <&gcc PCIE_PHY_CLK>;
 262                 clock-names = "core", "iface", "phy";
 263                 resets = <&gcc PCIE_ACLK_RESET>,
 264                          <&gcc PCIE_HCLK_RESET>,
 265                          <&gcc PCIE_POR_RESET>,
 266                          <&gcc PCIE_PCI_RESET>,
 267                          <&gcc PCIE_PHY_RESET>;
 268                 reset-names = "axi", "ahb", "por", "pci", "phy";
 269                 pinctrl-0 = <&pcie_pins_default>;
 270                 pinctrl-names = "default";
 271         };
 272
 273 * Example for apq8084
 274         pcie0@fc520000 {
 275                 compatible = "qcom,pcie-apq8084", "snps,dw-pcie";
 276                 reg = <0xfc520000 0x2000>,
 277                       <0xff000000 0x1000>,
 278                       <0xff001000 0x1000>,
 279                       <0xff002000 0x2000>;
 280                 reg-names = "parf", "dbi", "elbi", "config";
 281                 device_type = "pci";
 282                 linux,pci-domain = <0>;
 283                 bus-range = <0x00 0xff>;
 284                 num-lanes = <1>;
 285                 #address-cells = <3>;
 286                 #size-cells = <2>;
 287                 ranges = <0x81000000 0 0          0xff200000 0 0x00100000   /* I/O */
 288                           0x82000000 0 0x00300000 0xff300000 0 0x00d00000>; /* memory */
 289                 interrupts = <GIC_SPI 243 IRQ_TYPE_NONE>;
 290                 interrupt-names = "msi";
 291                 #interrupt-cells = <1>;
 292                 interrupt-map-mask = <0 0 0 0x7>;
 293                 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 294                                 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 295                                 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 296                                 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 297                 clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
 298                          <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
 299                          <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
 300                          <&gcc GCC_PCIE_0_AUX_CLK>;
 301                 clock-names = "iface", "master_bus", "slave_bus", "aux";
 302                 resets = <&gcc GCC_PCIE_0_BCR>;
 303                 reset-names = "core";
 304                 power-domains = <&gcc PCIE0_GDSC>;
 305                 vdda-supply = <&pma8084_l3>;
 306                 phys = <&pciephy0>;
 307                 phy-names = "pciephy";
 308                 perst-gpio = <&tlmm 70 GPIO_ACTIVE_LOW>;
 309                 pinctrl-0 = <&pcie0_pins_default>;
 310                 pinctrl-names = "default";
 311         };