Documentation/devicetree/bindings/pci/qcom,pcie.txt

   1 * Qualcomm PCI express root complex
   2
   3 - compatible:
   4         Usage: required
   5         Value type: <stringlist>
   6         Definition: Value should contain
   7                         - "qcom,pcie-ipq8064" for ipq8064
   8                         - "qcom,pcie-apq8064" for apq8064
   9                         - "qcom,pcie-apq8084" for apq8084
  10                         - "qcom,pcie-msm8996" for msm8996 or apq8096
  11                         - "qcom,pcie-ipq4019" for ipq4019
  12                         - "qcom,pcie-ipq8074" for ipq8074
  13
  14 - reg:
  15         Usage: required
  16         Value type: <prop-encoded-array>
  17         Definition: Register ranges as listed in the reg-names property
  18
  19 - reg-names:
  20         Usage: required
  21         Value type: <stringlist>
  22         Definition: Must include the following entries
  23                         - "parf"   Qualcomm specific registers
  24                         - "dbi"    DesignWare PCIe registers
  25                         - "elbi"   External local bus interface registers
  26                         - "config" PCIe configuration space
  27
  28 - device_type:
  29         Usage: required
  30         Value type: <string>
  31         Definition: Should be "pci". As specified in designware-pcie.txt
  32
  33 - #address-cells:
  34         Usage: required
  35         Value type: <u32>
  36         Definition: Should be 3. As specified in designware-pcie.txt
  37
  38 - #size-cells:
  39         Usage: required
  40         Value type: <u32>
  41         Definition: Should be 2. As specified in designware-pcie.txt
  42
  43 - ranges:
  44         Usage: required
  45         Value type: <prop-encoded-array>
  46         Definition: As specified in designware-pcie.txt
  47
  48 - interrupts:
  49         Usage: required
  50         Value type: <prop-encoded-array>
  51         Definition: MSI interrupt
  52
  53 - interrupt-names:
  54         Usage: required
  55         Value type: <stringlist>
  56         Definition: Should contain "msi"
  57
  58 - #interrupt-cells:
  59         Usage: required
  60         Value type: <u32>
  61         Definition: Should be 1. As specified in designware-pcie.txt
  62
  63 - interrupt-map-mask:
  64         Usage: required
  65         Value type: <prop-encoded-array>
  66         Definition: As specified in designware-pcie.txt
  67
  68 - interrupt-map:
  69         Usage: required
  70         Value type: <prop-encoded-array>
  71         Definition: As specified in designware-pcie.txt
  72
  73 - clocks:
  74         Usage: required
  75         Value type: <prop-encoded-array>
  76         Definition: List of phandle and clock specifier pairs as listed
  77                     in clock-names property
  78
  79 - clock-names:
  80         Usage: required
  81         Value type: <stringlist>
  82         Definition: Should contain the following entries
  83                         - "iface"       Configuration AHB clock
  84
  85 - clock-names:
  86         Usage: required for ipq/apq8064
  87         Value type: <stringlist>
  88         Definition: Should contain the following entries
  89                         - "core"        Clocks the pcie hw block
  90                         - "phy"         Clocks the pcie PHY block
  91 - clock-names:
  92         Usage: required for apq8084/ipq4019
  93         Value type: <stringlist>
  94         Definition: Should contain the following entries
  95                         - "aux"         Auxiliary (AUX) clock
  96                         - "bus_master"  Master AXI clock
  97                         - "bus_slave"   Slave AXI clock
  98
  99 - clock-names:
 100         Usage: required for msm8996/apq8096
 101         Value type: <stringlist>
 102         Definition: Should contain the following entries
 103                         - "pipe"        Pipe Clock driving internal logic
 104                         - "aux"         Auxiliary (AUX) clock
 105                         - "cfg"         Configuration clock
 106                         - "bus_master"  Master AXI clock
 107                         - "bus_slave"   Slave AXI clock
 108
 109 - clock-names:
 110         Usage: required for ipq8074
 111         Value type: <stringlist>
 112         Definition: Should contain the following entries
 113                         - "iface"       PCIe to SysNOC BIU clock
 114                         - "axi_m"       AXI Master clock
 115                         - "axi_s"       AXI Slave clock
 116                         - "ahb"         AHB clock
 117                         - "aux"         Auxiliary clock
 118
 119 - resets:
 120         Usage: required
 121         Value type: <prop-encoded-array>
 122         Definition: List of phandle and reset specifier pairs as listed
 123                     in reset-names property
 124
 125 - reset-names:
 126         Usage: required for ipq/apq8064
 127         Value type: <stringlist>
 128         Definition: Should contain the following entries
 129                         - "axi"  AXI reset
 130                         - "ahb"  AHB reset
 131                         - "por"  POR reset
 132                         - "pci"  PCI reset
 133                         - "phy"  PHY reset
 134
 135 - reset-names:
 136         Usage: required for apq8084
 137         Value type: <stringlist>
 138         Definition: Should contain the following entries
 139                         - "core" Core reset
 140
 141 - reset-names:
 142         Usage: required for ipq/apq8064
 143         Value type: <stringlist>
 144         Definition: Should contain the following entries
 145                         - "axi_m"               AXI master reset
 146                         - "axi_s"               AXI slave reset
 147                         - "pipe"                PIPE reset
 148                         - "axi_m_vmid"          VMID reset
 149                         - "axi_s_xpu"           XPU reset
 150                         - "parf"                PARF reset
 151                         - "phy"                 PHY reset
 152                         - "axi_m_sticky"        AXI sticky reset
 153                         - "pipe_sticky"         PIPE sticky reset
 154                         - "pwr"                 PWR reset
 155                         - "ahb"                 AHB reset
 156                         - "phy_ahb"             PHY AHB reset
 157
 158 - reset-names:
 159         Usage: required for ipq8074
 160         Value type: <stringlist>
 161         Definition: Should contain the following entries
 162                         - "pipe"                PIPE reset
 163                         - "sleep"               Sleep reset
 164                         - "sticky"              Core Sticky reset
 165                         - "axi_m"               AXI Master reset
 166                         - "axi_s"               AXI Slave reset
 167                         - "ahb"                 AHB Reset
 168                         - "axi_m_sticky"        AXI Master Sticky reset
 169
 170 - power-domains:
 171         Usage: required for apq8084 and msm8996/apq8096
 172         Value type: <prop-encoded-array>
 173         Definition: A phandle and power domain specifier pair to the
 174                     power domain which is responsible for collapsing
 175                     and restoring power to the peripheral
 176
 177 - vdda-supply:
 178         Usage: required
 179         Value type: <phandle>
 180         Definition: A phandle to the core analog power supply
 181
 182 - vdda_phy-supply:
 183         Usage: required for ipq/apq8064
 184         Value type: <phandle>
 185         Definition: A phandle to the analog power supply for PHY
 186
 187 - vdda_refclk-supply:
 188         Usage: required for ipq/apq8064
 189         Value type: <phandle>
 190         Definition: A phandle to the analog power supply for IC which generates
 191                     reference clock
 192
 193 - phys:
 194         Usage: required for apq8084
 195         Value type: <phandle>
 196         Definition: List of phandle(s) as listed in phy-names property
 197
 198 - phy-names:
 199         Usage: required for apq8084
 200         Value type: <stringlist>
 201         Definition: Should contain "pciephy"
 202
 203 - <name>-gpios:
 204         Usage: optional
 205         Value type: <prop-encoded-array>
 206         Definition: List of phandle and GPIO specifier pairs. Should contain
 207                         - "perst-gpios" PCIe endpoint reset signal line
 208                         - "wake-gpios"  PCIe endpoint wake signal line
 209
 210 * Example for ipq/apq8064
 211         pcie@1b500000 {
 212                 compatible = "qcom,pcie-apq8064", "qcom,pcie-ipq8064", "snps,dw-pcie";
 213                 reg = <0x1b500000 0x1000
 214                        0x1b502000 0x80
 215                        0x1b600000 0x100
 216                        0x0ff00000 0x100000>;
 217                 reg-names = "dbi", "elbi", "parf", "config";
 218                 device_type = "pci";
 219                 linux,pci-domain = <0>;
 220                 bus-range = <0x00 0xff>;
 221                 num-lanes = <1>;
 222                 #address-cells = <3>;
 223                 #size-cells = <2>;
 224                 ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000   /* I/O */
 225                           0x82000000 0 0 0x08000000 0 0x07e00000>; /* memory */
 226                 interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>;
 227                 interrupt-names = "msi";
 228                 #interrupt-cells = <1>;
 229                 interrupt-map-mask = <0 0 0 0x7>;
 230                 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 231                                 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 232                                 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 233                                 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 234                 clocks = <&gcc PCIE_A_CLK>,
 235                          <&gcc PCIE_H_CLK>,
 236                          <&gcc PCIE_PHY_CLK>;
 237                 clock-names = "core", "iface", "phy";
 238                 resets = <&gcc PCIE_ACLK_RESET>,
 239                          <&gcc PCIE_HCLK_RESET>,
 240                          <&gcc PCIE_POR_RESET>,
 241                          <&gcc PCIE_PCI_RESET>,
 242                          <&gcc PCIE_PHY_RESET>;
 243                 reset-names = "axi", "ahb", "por", "pci", "phy";
 244                 pinctrl-0 = <&pcie_pins_default>;
 245                 pinctrl-names = "default";
 246         };
 247
 248 * Example for apq8084
 249         pcie0@fc520000 {
 250                 compatible = "qcom,pcie-apq8084", "snps,dw-pcie";
 251                 reg = <0xfc520000 0x2000>,
 252                       <0xff000000 0x1000>,
 253                       <0xff001000 0x1000>,
 254                       <0xff002000 0x2000>;
 255                 reg-names = "parf", "dbi", "elbi", "config";
 256                 device_type = "pci";
 257                 linux,pci-domain = <0>;
 258                 bus-range = <0x00 0xff>;
 259                 num-lanes = <1>;
 260                 #address-cells = <3>;
 261                 #size-cells = <2>;
 262                 ranges = <0x81000000 0 0          0xff200000 0 0x00100000   /* I/O */
 263                           0x82000000 0 0x00300000 0xff300000 0 0x00d00000>; /* memory */
 264                 interrupts = <GIC_SPI 243 IRQ_TYPE_NONE>;
 265                 interrupt-names = "msi";
 266                 #interrupt-cells = <1>;
 267                 interrupt-map-mask = <0 0 0 0x7>;
 268                 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 269                                 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 270                                 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 271                                 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 272                 clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
 273                          <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
 274                          <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
 275                          <&gcc GCC_PCIE_0_AUX_CLK>;
 276                 clock-names = "iface", "master_bus", "slave_bus", "aux";
 277                 resets = <&gcc GCC_PCIE_0_BCR>;
 278                 reset-names = "core";
 279                 power-domains = <&gcc PCIE0_GDSC>;
 280                 vdda-supply = <&pma8084_l3>;
 281                 phys = <&pciephy0>;
 282                 phy-names = "pciephy";
 283                 perst-gpio = <&tlmm 70 GPIO_ACTIVE_LOW>;
 284                 pinctrl-0 = <&pcie0_pins_default>;
 285                 pinctrl-names = "default";
 286         };