1 Amlogic Meson AXG DWC PCIE SoC controller
3 Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core.
4 It shares common functions with the PCIe DesignWare core driver and
5 inherits common properties defined in
6 Documentation/devicetree/bindings/pci/designware-pci.txt.
8 Additional properties are described here:
12 should contain "amlogic,axg-pcie" to identify the core.
14 should contain the configuration address space.
16 - "elbi" External local bus interface registers
17 - "cfg" Meson specific registers
18 - "phy" Meson PCIE PHY registers
19 - "config" PCIe configuration space
20 - reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal.
21 - clocks: Must contain an entry for each entry in clock-names.
22 - clock-names: Must include the following entries:
23 - "pclk" PCIe GEN 100M PLL clock
24 - "port" PCIe_x(A or B) RC clock gate
25 - "general" PCIe Phy clock
26 - "mipi" PCIe_x(A or B) 100M ref clock gate
27 - resets: phandle to the reset lines.
28 - reset-names: must contain "phy" "port" and "apb"
29 - "phy" Share PHY reset
30 - "port" Port A or B reset
31 - "apb" Share APB reset
33 should be "pci". As specified in designware-pcie.txt
36 Example configuration:
39 compatible = "amlogic,axg-pcie", "snps,dw-pcie";
40 reg = <0x0 0xf9800000 0x0 0x400000
41 0x0 0xff646000 0x0 0x2000
42 0x0 0xff644000 0x0 0x2000
43 0x0 0xf9f00000 0x0 0x100000>;
44 reg-names = "elbi", "cfg", "phy", "config";
45 reset-gpios = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>;
46 interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>;
47 #interrupt-cells = <1>;
48 interrupt-map-mask = <0 0 0 0>;
49 interrupt-map = <0 0 0 0 &gic GIC_SPI 179 IRQ_TYPE_EDGE_RISING>;
50 bus-range = <0x0 0xff>;
54 ranges = <0x82000000 0 0 0x0 0xf9c00000 0 0x00300000>;
56 clocks = <&clkc CLKID_USB
57 &clkc CLKID_MIPI_ENABLE
59 &clkc CLKID_PCIE_CML_EN0>;
60 clock-names = "general",
64 resets = <&reset RESET_PCIE_PHY>,
65 <&reset RESET_PCIE_A>,
66 <&reset RESET_PCIE_APB>;