Documentation/devicetree/bindings/nvmem/imx-ocotp.txt

   1 Freescale i.MX6 On-Chip OTP Controller (OCOTP) device tree bindings
   2
   3 This binding represents the on-chip eFuse OTP controller found on
   4 i.MX6Q/D, i.MX6DL/S, i.MX6SL, i.MX6SX, i.MX6UL, i.MX6ULL/ULZ and i.MX6SLL SoCs.
   5
   6 Required properties:
   7 - compatible: should be one of
   8         "fsl,imx6q-ocotp" (i.MX6Q/D/DL/S),
   9         "fsl,imx6sl-ocotp" (i.MX6SL), or
  10         "fsl,imx6sx-ocotp" (i.MX6SX),
  11         "fsl,imx6ul-ocotp" (i.MX6UL),
  12         "fsl,imx6ull-ocotp" (i.MX6ULL/ULZ),
  13         "fsl,imx7d-ocotp" (i.MX7D/S),
  14         "fsl,imx6sll-ocotp" (i.MX6SLL),
  15         "fsl,imx7ulp-ocotp" (i.MX7ULP),
  16         followed by "syscon".
  17 - #address-cells : Should be 1
  18 - #size-cells : Should be 1
  19 - reg: Should contain the register base and length.
  20 - clocks: Should contain a phandle pointing to the gated peripheral clock.
  21
  22 Optional properties:
  23 - read-only: disable write access
  24
  25 Optional Child nodes:
  26
  27 - Data cells of ocotp:
  28   Detailed bindings are described in bindings/nvmem/nvmem.txt
  29
  30 Example:
  31         ocotp: ocotp@21bc000 {
  32                 #address-cells = <1>;
  33                 #size-cells = <1>;
  34                 compatible = "fsl,imx6sx-ocotp", "syscon";
  35                 reg = <0x021bc000 0x4000>;
  36                 clocks = <&clks IMX6SX_CLK_OCOTP>;
  37
  38                 tempmon_calib: calib@38 {
  39                         reg = <0x38 4>;
  40                 };
  41
  42                 tempmon_temp_grade: temp-grade@20 {
  43                         reg = <0x20 4>;
  44                 };
  45         };