Documentation/devicetree/bindings/net/mdio-mux.txt

   1 Common MDIO bus multiplexer/switch properties.
   2
   3 An MDIO bus multiplexer/switch will have several child busses that are
   4 numbered uniquely in a device dependent manner.  The nodes for an MDIO
   5 bus multiplexer/switch will have one child node for each child bus.
   6
   7 Required properties:
   8 - mdio-parent-bus : phandle to the parent MDIO bus.
   9 - #address-cells = <1>;
  10 - #size-cells = <0>;
  11
  12 Optional properties:
  13 - Other properties specific to the multiplexer/switch hardware.
  14
  15 Required properties for child nodes:
  16 - #address-cells = <1>;
  17 - #size-cells = <0>;
  18 - reg : The sub-bus number.
  19
  20
  21 Example :
  22
  23         /* The parent MDIO bus. */
  24         smi1: mdio@1180000001900 {
  25                 compatible = "cavium,octeon-3860-mdio";
  26                 #address-cells = <1>;
  27                 #size-cells = <0>;
  28                 reg = <0x11800 0x00001900 0x0 0x40>;
  29         };
  30
  31         /*
  32            An NXP sn74cbtlv3253 dual 1-of-4 switch controlled by a
  33            pair of GPIO lines.  Child busses 2 and 3 populated with 4
  34            PHYs each.
  35          */
  36         mdio-mux {
  37                 compatible = "mdio-mux-gpio";
  38                 gpios = <&gpio1 3 0>, <&gpio1 4 0>;
  39                 mdio-parent-bus = <&smi1>;
  40                 #address-cells = <1>;
  41                 #size-cells = <0>;
  42
  43                 mdio@2 {
  44                         reg = <2>;
  45                         #address-cells = <1>;
  46                         #size-cells = <0>;
  47
  48                         phy11: ethernet-phy@1 {
  49                                 reg = <1>;
  50                                 marvell,reg-init = <3 0x10 0 0x5777>,
  51                                         <3 0x11 0 0x00aa>,
  52                                         <3 0x12 0 0x4105>,
  53                                         <3 0x13 0 0x0a60>;
  54                                 interrupt-parent = <&gpio>;
  55                                 interrupts = <10 8>; /* Pin 10, active low */
  56                         };
  57                         phy12: ethernet-phy@2 {
  58                                 reg = <2>;
  59                                 marvell,reg-init = <3 0x10 0 0x5777>,
  60                                         <3 0x11 0 0x00aa>,
  61                                         <3 0x12 0 0x4105>,
  62                                         <3 0x13 0 0x0a60>;
  63                                 interrupt-parent = <&gpio>;
  64                                 interrupts = <10 8>; /* Pin 10, active low */
  65                         };
  66                         phy13: ethernet-phy@3 {
  67                                 reg = <3>;
  68                                 marvell,reg-init = <3 0x10 0 0x5777>,
  69                                         <3 0x11 0 0x00aa>,
  70                                         <3 0x12 0 0x4105>,
  71                                         <3 0x13 0 0x0a60>;
  72                                 interrupt-parent = <&gpio>;
  73                                 interrupts = <10 8>; /* Pin 10, active low */
  74                         };
  75                         phy14: ethernet-phy@4 {
  76                                 reg = <4>;
  77                                 marvell,reg-init = <3 0x10 0 0x5777>,
  78                                         <3 0x11 0 0x00aa>,
  79                                         <3 0x12 0 0x4105>,
  80                                         <3 0x13 0 0x0a60>;
  81                                 interrupt-parent = <&gpio>;
  82                                 interrupts = <10 8>; /* Pin 10, active low */
  83                         };
  84                 };
  85
  86                 mdio@3 {
  87                         reg = <3>;
  88                         #address-cells = <1>;
  89                         #size-cells = <0>;
  90
  91                         phy21: ethernet-phy@1 {
  92                                 reg = <1>;
  93                                 marvell,reg-init = <3 0x10 0 0x5777>,
  94                                         <3 0x11 0 0x00aa>,
  95                                         <3 0x12 0 0x4105>,
  96                                         <3 0x13 0 0x0a60>;
  97                                 interrupt-parent = <&gpio>;
  98                                 interrupts = <12 8>; /* Pin 12, active low */
  99                         };
 100                         phy22: ethernet-phy@2 {
 101                                 reg = <2>;
 102                                 marvell,reg-init = <3 0x10 0 0x5777>,
 103                                         <3 0x11 0 0x00aa>,
 104                                         <3 0x12 0 0x4105>,
 105                                         <3 0x13 0 0x0a60>;
 106                                 interrupt-parent = <&gpio>;
 107                                 interrupts = <12 8>; /* Pin 12, active low */
 108                         };
 109                         phy23: ethernet-phy@3 {
 110                                 reg = <3>;
 111                                 marvell,reg-init = <3 0x10 0 0x5777>,
 112                                         <3 0x11 0 0x00aa>,
 113                                         <3 0x12 0 0x4105>,
 114                                         <3 0x13 0 0x0a60>;
 115                                 interrupt-parent = <&gpio>;
 116                                 interrupts = <12 8>; /* Pin 12, active low */
 117                         };
 118                         phy24: ethernet-phy@4 {
 119                                 reg = <4>;
 120                                 marvell,reg-init = <3 0x10 0 0x5777>,
 121                                         <3 0x11 0 0x00aa>,
 122                                         <3 0x12 0 0x4105>,
 123                                         <3 0x13 0 0x0a60>;
 124                                 interrupt-parent = <&gpio>;
 125                                 interrupts = <12 8>; /* Pin 12, active low */
 126                         };
 127                 };
 128         };