Documentation/devicetree/bindings/net/dwmac-sun8i.txt

   1 * Allwinner sun8i GMAC ethernet controller
   2
   3 This device is a platform glue layer for stmmac.
   4 Please see stmmac.txt for the other unchanged properties.
   5
   6 Required properties:
   7 - compatible: must be one of the following string:
   8                 "allwinner,sun8i-a83t-emac"
   9                 "allwinner,sun8i-h3-emac"
  10                 "allwinner,sun8i-r40-gmac"
  11                 "allwinner,sun8i-v3s-emac"
  12                 "allwinner,sun50i-a64-emac"
  13                 "allwinner,sun50i-h6-emac", "allwinner-sun50i-a64-emac"
  14 - reg: address and length of the register for the device.
  15 - interrupts: interrupt for the device
  16 - interrupt-names: must be "macirq"
  17 - clocks: A phandle to the reference clock for this device
  18 - clock-names: must be "stmmaceth"
  19 - resets: A phandle to the reset control for this device
  20 - reset-names: must be "stmmaceth"
  21 - phy-mode: See ethernet.txt
  22 - phy-handle: See ethernet.txt
  23 - syscon: A phandle to the device containing the EMAC or GMAC clock register
  24
  25 Optional properties:
  26 - allwinner,tx-delay-ps: TX clock delay chain value in ps.
  27                          Range is 0-700. Default is 0.
  28                          Unavailable for allwinner,sun8i-r40-gmac
  29 - allwinner,rx-delay-ps: RX clock delay chain value in ps.
  30                          Range is 0-3100. Default is 0.
  31                          Range is 0-700 for allwinner,sun8i-r40-gmac
  32 Both delay properties need to be a multiple of 100. They control the
  33 clock delay for external RGMII PHY. They do not apply to the internal
  34 PHY or external non-RGMII PHYs.
  35
  36 Optional properties for the following compatibles:
  37   - "allwinner,sun8i-h3-emac",
  38   - "allwinner,sun8i-v3s-emac":
  39 - allwinner,leds-active-low: EPHY LEDs are active low
  40
  41 Required child node of emac:
  42 - mdio bus node: should be named mdio with compatible "snps,dwmac-mdio"
  43
  44 Required properties of the mdio node:
  45 - #address-cells: shall be 1
  46 - #size-cells: shall be 0
  47
  48 The device node referenced by "phy" or "phy-handle" must be a child node
  49 of the mdio node. See phy.txt for the generic PHY bindings.
  50
  51 The following compatibles require that the emac node have a mdio-mux child
  52 node called "mdio-mux":
  53   - "allwinner,sun8i-h3-emac"
  54   - "allwinner,sun8i-v3s-emac":
  55 Required properties for the mdio-mux node:
  56   - compatible = "allwinner,sun8i-h3-mdio-mux"
  57   - mdio-parent-bus: a phandle to EMAC mdio
  58   - one child mdio for the integrated mdio with the compatible
  59     "allwinner,sun8i-h3-mdio-internal"
  60   - one child mdio for the external mdio if present (V3s have none)
  61 Required properties for the mdio-mux children node:
  62   - reg: 1 for internal MDIO bus, 2 for external MDIO bus
  63
  64 The following compatibles require a PHY node representing the integrated
  65 PHY, under the integrated MDIO bus node if an mdio-mux node is used:
  66   - "allwinner,sun8i-h3-emac",
  67   - "allwinner,sun8i-v3s-emac":
  68
  69 Additional information regarding generic multiplexer properties can be found
  70 at Documentation/devicetree/bindings/net/mdio-mux.txt
  71
  72 Required properties of the integrated phy node:
  73 - clocks: a phandle to the reference clock for the EPHY
  74 - resets: a phandle to the reset control for the EPHY
  75 - Must be a child of the integrated mdio
  76
  77 Example with integrated PHY:
  78 emac: ethernet@1c0b000 {
  79         compatible = "allwinner,sun8i-h3-emac";
  80         syscon = <&syscon>;
  81         reg = <0x01c0b000 0x104>;
  82         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
  83         interrupt-names = "macirq";
  84         resets = <&ccu RST_BUS_EMAC>;
  85         reset-names = "stmmaceth";
  86         clocks = <&ccu CLK_BUS_EMAC>;
  87         clock-names = "stmmaceth";
  88
  89         phy-handle = <&int_mii_phy>;
  90         phy-mode = "mii";
  91         allwinner,leds-active-low;
  92
  93         mdio: mdio {
  94                 #address-cells = <1>;
  95                 #size-cells = <0>;
  96                 compatible = "snps,dwmac-mdio";
  97         };
  98
  99         mdio-mux {
 100                 compatible = "mdio-mux", "allwinner,sun8i-h3-mdio-mux";
 101                 #address-cells = <1>;
 102                 #size-cells = <0>;
 103
 104                 mdio-parent-bus = <&mdio>;
 105
 106                 int_mdio: mdio@1 {
 107                         compatible = "allwinner,sun8i-h3-mdio-internal";
 108                         reg = <1>;
 109                         #address-cells = <1>;
 110                         #size-cells = <0>;
 111                         int_mii_phy: ethernet-phy@1 {
 112                                 reg = <1>;
 113                                 clocks = <&ccu CLK_BUS_EPHY>;
 114                                 resets = <&ccu RST_BUS_EPHY>;
 115                                 phy-is-integrated;
 116                         };
 117                 };
 118                 ext_mdio: mdio@2 {
 119                         reg = <2>;
 120                         #address-cells = <1>;
 121                         #size-cells = <0>;
 122                 };
 123         };
 124 };
 125
 126 Example with external PHY:
 127 emac: ethernet@1c0b000 {
 128         compatible = "allwinner,sun8i-h3-emac";
 129         syscon = <&syscon>;
 130         reg = <0x01c0b000 0x104>;
 131         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 132         interrupt-names = "macirq";
 133         resets = <&ccu RST_BUS_EMAC>;
 134         reset-names = "stmmaceth";
 135         clocks = <&ccu CLK_BUS_EMAC>;
 136         clock-names = "stmmaceth";
 137
 138         phy-handle = <&ext_rgmii_phy>;
 139         phy-mode = "rgmii";
 140         allwinner,leds-active-low;
 141
 142         mdio: mdio {
 143                 #address-cells = <1>;
 144                 #size-cells = <0>;
 145                 compatible = "snps,dwmac-mdio";
 146         };
 147
 148         mdio-mux {
 149                 compatible = "allwinner,sun8i-h3-mdio-mux";
 150                 #address-cells = <1>;
 151                 #size-cells = <0>;
 152
 153                 mdio-parent-bus = <&mdio>;
 154
 155                 int_mdio: mdio@1 {
 156                         compatible = "allwinner,sun8i-h3-mdio-internal";
 157                         reg = <1>;
 158                         #address-cells = <1>;
 159                         #size-cells = <0>;
 160                         int_mii_phy: ethernet-phy@1 {
 161                                 reg = <1>;
 162                                 clocks = <&ccu CLK_BUS_EPHY>;
 163                                 resets = <&ccu RST_BUS_EPHY>;
 164                         };
 165                 };
 166                 ext_mdio: mdio@2 {
 167                         reg = <2>;
 168                         #address-cells = <1>;
 169                         #size-cells = <0>;
 170                         ext_rgmii_phy: ethernet-phy@1 {
 171                                 reg = <1>;
 172                         };
 173                 }:
 174         };
 175 };
 176
 177 Example with SoC without integrated PHY
 178
 179 emac: ethernet@1c0b000 {
 180         compatible = "allwinner,sun8i-a83t-emac";
 181         syscon = <&syscon>;
 182         reg = <0x01c0b000 0x104>;
 183         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 184         interrupt-names = "macirq";
 185         resets = <&ccu RST_BUS_EMAC>;
 186         reset-names = "stmmaceth";
 187         clocks = <&ccu CLK_BUS_EMAC>;
 188         clock-names = "stmmaceth";
 189
 190         phy-handle = <&ext_rgmii_phy>;
 191         phy-mode = "rgmii";
 192
 193         mdio: mdio {
 194                 compatible = "snps,dwmac-mdio";
 195                 #address-cells = <1>;
 196                 #size-cells = <0>;
 197                 ext_rgmii_phy: ethernet-phy@1 {
 198                         reg = <1>;
 199                 };
 200         };
 201 };