Documentation/devicetree/bindings/net/dwmac-sun8i.txt

   1 * Allwinner sun8i GMAC ethernet controller
   2
   3 This device is a platform glue layer for stmmac.
   4 Please see stmmac.txt for the other unchanged properties.
   5
   6 Required properties:
   7 - compatible: must be one of the following string:
   8                 "allwinner,sun8i-a83t-emac"
   9                 "allwinner,sun8i-h3-emac"
  10                 "allwinner,sun8i-v3s-emac"
  11                 "allwinner,sun50i-a64-emac"
  12 - reg: address and length of the register for the device.
  13 - interrupts: interrupt for the device
  14 - interrupt-names: must be "macirq"
  15 - clocks: A phandle to the reference clock for this device
  16 - clock-names: must be "stmmaceth"
  17 - resets: A phandle to the reset control for this device
  18 - reset-names: must be "stmmaceth"
  19 - phy-mode: See ethernet.txt
  20 - phy-handle: See ethernet.txt
  21 - #address-cells: shall be 1
  22 - #size-cells: shall be 0
  23 - syscon: A phandle to the syscon of the SoC with one of the following
  24  compatible string:
  25   - allwinner,sun8i-h3-system-controller
  26   - allwinner,sun8i-v3s-system-controller
  27   - allwinner,sun50i-a64-system-controller
  28   - allwinner,sun8i-a83t-system-controller
  29
  30 Optional properties:
  31 - allwinner,tx-delay-ps: TX clock delay chain value in ps. Range value is 0-700. Default is 0)
  32 - allwinner,rx-delay-ps: RX clock delay chain value in ps. Range value is 0-3100. Default is 0)
  33 Both delay properties need to be a multiple of 100. They control the delay for
  34 external PHY.
  35
  36 Optional properties for the following compatibles:
  37   - "allwinner,sun8i-h3-emac",
  38   - "allwinner,sun8i-v3s-emac":
  39 - allwinner,leds-active-low: EPHY LEDs are active low
  40
  41 Required child node of emac:
  42 - mdio bus node: should be named mdio with compatible "snps,dwmac-mdio"
  43
  44 Required properties of the mdio node:
  45 - #address-cells: shall be 1
  46 - #size-cells: shall be 0
  47
  48 The device node referenced by "phy" or "phy-handle" must be a child node
  49 of the mdio node. See phy.txt for the generic PHY bindings.
  50
  51 The following compatibles require that the emac node have a mdio-mux child
  52 node called "mdio-mux":
  53   - "allwinner,sun8i-h3-emac"
  54   - "allwinner,sun8i-v3s-emac":
  55 Required properties for the mdio-mux node:
  56   - compatible = "allwinner,sun8i-h3-mdio-mux"
  57   - mdio-parent-bus: a phandle to EMAC mdio
  58   - one child mdio for the integrated mdio with the compatible
  59     "allwinner,sun8i-h3-mdio-internal"
  60   - one child mdio for the external mdio if present (V3s have none)
  61 Required properties for the mdio-mux children node:
  62   - reg: 1 for internal MDIO bus, 2 for external MDIO bus
  63
  64 The following compatibles require a PHY node representing the integrated
  65 PHY, under the integrated MDIO bus node if an mdio-mux node is used:
  66   - "allwinner,sun8i-h3-emac",
  67   - "allwinner,sun8i-v3s-emac":
  68
  69 Additional information regarding generic multiplexer properties can be found
  70 at Documentation/devicetree/bindings/net/mdio-mux.txt
  71
  72 Required properties of the integrated phy node:
  73 - clocks: a phandle to the reference clock for the EPHY
  74 - resets: a phandle to the reset control for the EPHY
  75 - Must be a child of the integrated mdio
  76
  77 Example with integrated PHY:
  78 emac: ethernet@1c0b000 {
  79         compatible = "allwinner,sun8i-h3-emac";
  80         syscon = <&syscon>;
  81         reg = <0x01c0b000 0x104>;
  82         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
  83         interrupt-names = "macirq";
  84         resets = <&ccu RST_BUS_EMAC>;
  85         reset-names = "stmmaceth";
  86         clocks = <&ccu CLK_BUS_EMAC>;
  87         clock-names = "stmmaceth";
  88         #address-cells = <1>;
  89         #size-cells = <0>;
  90
  91         phy-handle = <&int_mii_phy>;
  92         phy-mode = "mii";
  93         allwinner,leds-active-low;
  94
  95         mdio: mdio {
  96                 #address-cells = <1>;
  97                 #size-cells = <0>;
  98                 compatible = "snps,dwmac-mdio";
  99         };
 100
 101         mdio-mux {
 102                 compatible = "mdio-mux", "allwinner,sun8i-h3-mdio-mux";
 103                 #address-cells = <1>;
 104                 #size-cells = <0>;
 105
 106                 mdio-parent-bus = <&mdio>;
 107
 108                 int_mdio: mdio@1 {
 109                         compatible = "allwinner,sun8i-h3-mdio-internal";
 110                         reg = <1>;
 111                         #address-cells = <1>;
 112                         #size-cells = <0>;
 113                         int_mii_phy: ethernet-phy@1 {
 114                                 reg = <1>;
 115                                 clocks = <&ccu CLK_BUS_EPHY>;
 116                                 resets = <&ccu RST_BUS_EPHY>;
 117                                 phy-is-integrated;
 118                         };
 119                 };
 120                 ext_mdio: mdio@2 {
 121                         reg = <2>;
 122                         #address-cells = <1>;
 123                         #size-cells = <0>;
 124                 };
 125         };
 126 };
 127
 128 Example with external PHY:
 129 emac: ethernet@1c0b000 {
 130         compatible = "allwinner,sun8i-h3-emac";
 131         syscon = <&syscon>;
 132         reg = <0x01c0b000 0x104>;
 133         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 134         interrupt-names = "macirq";
 135         resets = <&ccu RST_BUS_EMAC>;
 136         reset-names = "stmmaceth";
 137         clocks = <&ccu CLK_BUS_EMAC>;
 138         clock-names = "stmmaceth";
 139         #address-cells = <1>;
 140         #size-cells = <0>;
 141
 142         phy-handle = <&ext_rgmii_phy>;
 143         phy-mode = "rgmii";
 144         allwinner,leds-active-low;
 145
 146         mdio: mdio {
 147                 #address-cells = <1>;
 148                 #size-cells = <0>;
 149                 compatible = "snps,dwmac-mdio";
 150         };
 151
 152         mdio-mux {
 153                 compatible = "allwinner,sun8i-h3-mdio-mux";
 154                 #address-cells = <1>;
 155                 #size-cells = <0>;
 156
 157                 mdio-parent-bus = <&mdio>;
 158
 159                 int_mdio: mdio@1 {
 160                         compatible = "allwinner,sun8i-h3-mdio-internal";
 161                         reg = <1>;
 162                         #address-cells = <1>;
 163                         #size-cells = <0>;
 164                         int_mii_phy: ethernet-phy@1 {
 165                                 reg = <1>;
 166                                 clocks = <&ccu CLK_BUS_EPHY>;
 167                                 resets = <&ccu RST_BUS_EPHY>;
 168                         };
 169                 };
 170                 ext_mdio: mdio@2 {
 171                         reg = <2>;
 172                         #address-cells = <1>;
 173                         #size-cells = <0>;
 174                         ext_rgmii_phy: ethernet-phy@1 {
 175                                 reg = <1>;
 176                         };
 177                 }:
 178         };
 179 };
 180
 181 Example with SoC without integrated PHY
 182
 183 emac: ethernet@1c0b000 {
 184         compatible = "allwinner,sun8i-a83t-emac";
 185         syscon = <&syscon>;
 186         reg = <0x01c0b000 0x104>;
 187         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 188         interrupt-names = "macirq";
 189         resets = <&ccu RST_BUS_EMAC>;
 190         reset-names = "stmmaceth";
 191         clocks = <&ccu CLK_BUS_EMAC>;
 192         clock-names = "stmmaceth";
 193         #address-cells = <1>;
 194         #size-cells = <0>;
 195
 196         phy-handle = <&ext_rgmii_phy>;
 197         phy-mode = "rgmii";
 198
 199         mdio: mdio {
 200                 compatible = "snps,dwmac-mdio";
 201                 #address-cells = <1>;
 202                 #size-cells = <0>;
 203                 ext_rgmii_phy: ethernet-phy@1 {
 204                         reg = <1>;
 205                 };
 206         };
 207 };