Documentation/devicetree/bindings/net/dsa/dsa.txt

   1 Distributed Switch Architecture Device Tree Bindings
   2 ----------------------------------------------------
   3
   4 Two bindings exist, one of which has been deprecated due to
   5 limitations.
   6
   7 Current Binding
   8 ---------------
   9
  10 Switches are true Linux devices and can be probes by any means. Once
  11 probed, they register to the DSA framework, passing a node
  12 pointer. This node is expected to fulfil the following binding, and
  13 may contain additional properties as required by the device it is
  14 embedded within.
  15
  16 Required properties:
  17
  18 - ports         : A container for child nodes representing switch ports.
  19
  20 Optional properties:
  21
  22 - dsa,member    : A two element list indicates which DSA cluster, and position
  23                   within the cluster a switch takes. <0 0> is cluster 0,
  24                   switch 0. <0 1> is cluster 0, switch 1. <1 0> is cluster 1,
  25                   switch 0. A switch not part of any cluster (single device
  26                   hanging off a CPU port) must not specify this property
  27
  28 The ports container has the following properties
  29
  30 Required properties:
  31
  32 - #address-cells        : Must be 1
  33 - #size-cells           : Must be 0
  34
  35 Each port children node must have the following mandatory properties:
  36 - reg                   : Describes the port address in the switch
  37 - label                 : Describes the label associated with this port, which
  38                           will become the netdev name. Special labels are
  39                           "cpu" to indicate a CPU port and "dsa" to
  40                           indicate an uplink/downlink port between switches in
  41                           the cluster.
  42
  43 A port labelled "dsa" has the following mandatory property:
  44
  45 - link                  : Should be a list of phandles to other switch's DSA
  46                           port. This port is used as the outgoing port
  47                           towards the phandle ports. The full routing
  48                           information must be given, not just the one hop
  49                           routes to neighbouring switches.
  50
  51 A port labelled "cpu" has the following mandatory property:
  52
  53 - ethernet              : Should be a phandle to a valid Ethernet device node.
  54                           This host device is what the switch port is
  55                           connected to.
  56
  57 Port child nodes may also contain the following optional standardised
  58 properties, described in binding documents:
  59
  60 - phy-handle            : Phandle to a PHY on an MDIO bus. See
  61                           Documentation/devicetree/bindings/net/ethernet.txt
  62                           for details.
  63
  64 - phy-mode              : See
  65                           Documentation/devicetree/bindings/net/ethernet.txt
  66                           for details.
  67
  68 - fixed-link            : Fixed-link subnode describing a link to a non-MDIO
  69                           managed entity. See
  70                           Documentation/devicetree/bindings/net/fixed-link.txt
  71                           for details.
  72
  73 Example
  74
  75 The following example shows three switches on three MDIO busses,
  76 linked into one DSA cluster.
  77
  78 &mdio1 {
  79         #address-cells = <1>;
  80         #size-cells = <0>;
  81
  82         switch0: switch0@0 {
  83                 compatible = "marvell,mv88e6085";
  84                 #address-cells = <1>;
  85                 #size-cells = <0>;
  86                 reg = <0>;
  87
  88                 dsa,member = <0 0>;
  89
  90                 ports {
  91                         #address-cells = <1>;
  92                         #size-cells = <0>;
  93                         port@0 {
  94                                 reg = <0>;
  95                                 label = "lan0";
  96                         };
  97
  98                         port@1 {
  99                                 reg = <1>;
 100                                 label = "lan1";
 101                         };
 102
 103                         port@2 {
 104                                 reg = <2>;
 105                                 label = "lan2";
 106                         };
 107
 108                         switch0port5: port@5 {
 109                                 reg = <5>;
 110                                 label = "dsa";
 111                                 phy-mode = "rgmii-txid";
 112                                 link = <&switch1port6
 113                                         &switch2port9>;
 114                                 fixed-link {
 115                                         speed = <1000>;
 116                                         full-duplex;
 117                                 };
 118                         };
 119
 120                         port@6 {
 121                                 reg = <6>;
 122                                 label = "cpu";
 123                                 ethernet = <&fec1>;
 124                                 fixed-link {
 125                                         speed = <100>;
 126                                         full-duplex;
 127                                 };
 128                         };
 129                 };
 130         };
 131 };
 132
 133 &mdio2 {
 134         #address-cells = <1>;
 135         #size-cells = <0>;
 136
 137         switch1: switch1@0 {
 138                 compatible = "marvell,mv88e6085";
 139                 #address-cells = <1>;
 140                 #size-cells = <0>;
 141                 reg = <0>;
 142
 143                 dsa,member = <0 1>;
 144
 145                 ports {
 146                         #address-cells = <1>;
 147                         #size-cells = <0>;
 148                         port@0 {
 149                                 reg = <0>;
 150                                 label = "lan3";
 151                                 phy-handle = <&switch1phy0>;
 152                         };
 153
 154                         port@1 {
 155                                 reg = <1>;
 156                                 label = "lan4";
 157                                 phy-handle = <&switch1phy1>;
 158                         };
 159
 160                         port@2 {
 161                                 reg = <2>;
 162                                 label = "lan5";
 163                                 phy-handle = <&switch1phy2>;
 164                         };
 165
 166                         switch1port5: port@5 {
 167                                 reg = <5>;
 168                                 label = "dsa";
 169                                 link = <&switch2port9>;
 170                                 phy-mode = "rgmii-txid";
 171                                 fixed-link {
 172                                         speed = <1000>;
 173                                         full-duplex;
 174                                 };
 175                         };
 176
 177                         switch1port6: port@6 {
 178                                 reg = <6>;
 179                                 label = "dsa";
 180                                 phy-mode = "rgmii-txid";
 181                                 link = <&switch0port5>;
 182                                 fixed-link {
 183                                         speed = <1000>;
 184                                         full-duplex;
 185                                 };
 186                         };
 187                 };
 188                 mdio-bus {
 189                         #address-cells = <1>;
 190                         #size-cells = <0>;
 191                         switch1phy0: switch1phy0@0 {
 192                                 reg = <0>;
 193                         };
 194                         switch1phy1: switch1phy0@1 {
 195                                 reg = <1>;
 196                         };
 197                         switch1phy2: switch1phy0@2 {
 198                                 reg = <2>;
 199                         };
 200                 };
 201          };
 202 };
 203
 204 &mdio4 {
 205         #address-cells = <1>;
 206         #size-cells = <0>;
 207
 208         switch2: switch2@0 {
 209                 compatible = "marvell,mv88e6085";
 210                 #address-cells = <1>;
 211                 #size-cells = <0>;
 212                 reg = <0>;
 213
 214                 dsa,member = <0 2>;
 215
 216                 ports {
 217                         #address-cells = <1>;
 218                         #size-cells = <0>;
 219                         port@0 {
 220                                 reg = <0>;
 221                                 label = "lan6";
 222                         };
 223
 224                         port@1 {
 225                                 reg = <1>;
 226                                 label = "lan7";
 227                         };
 228
 229                         port@2 {
 230                                 reg = <2>;
 231                                 label = "lan8";
 232                         };
 233
 234                         port@3 {
 235                                 reg = <3>;
 236                                 label = "optical3";
 237                                 fixed-link {
 238                                         speed = <1000>;
 239                                         full-duplex;
 240                                         link-gpios = <&gpio6 2
 241                                               GPIO_ACTIVE_HIGH>;
 242                                 };
 243                         };
 244
 245                         port@4 {
 246                                 reg = <4>;
 247                                 label = "optical4";
 248                                 fixed-link {
 249                                         speed = <1000>;
 250                                         full-duplex;
 251                                         link-gpios = <&gpio6 3
 252                                               GPIO_ACTIVE_HIGH>;
 253                                 };
 254                         };
 255
 256                         switch2port9: port@9 {
 257                                 reg = <9>;
 258                                 label = "dsa";
 259                                 phy-mode = "rgmii-txid";
 260                                 link = <&switch1port5
 261                                         &switch0port5>;
 262                                 fixed-link {
 263                                         speed = <1000>;
 264                                         full-duplex;
 265                                 };
 266                         };
 267                 };
 268         };
 269 };
 270
 271 Deprecated Binding
 272 ------------------
 273
 274 The deprecated binding makes use of a platform device to represent the
 275 switches. The switches themselves are not Linux devices, and make use
 276 of an MDIO bus for management.
 277
 278 Required properties:
 279 - compatible            : Should be "marvell,dsa"
 280 - #address-cells        : Must be 2, first cell is the address on the MDIO bus
 281                           and second cell is the address in the switch tree.
 282                           Second cell is used only when cascading/chaining.
 283 - #size-cells           : Must be 0
 284 - dsa,ethernet          : Should be a phandle to a valid Ethernet device node
 285 - dsa,mii-bus           : Should be a phandle to a valid MDIO bus device node
 286
 287 Optional properties:
 288 - interrupts            : property with a value describing the switch
 289                           interrupt number (not supported by the driver)
 290
 291 A DSA node can contain multiple switch chips which are therefore child nodes of
 292 the parent DSA node. The maximum number of allowed child nodes is 4
 293 (DSA_MAX_SWITCHES).
 294 Each of these switch child nodes should have the following required properties:
 295
 296 - reg                   : Contains two fields. The first one describes the
 297                           address on the MII bus. The second is the switch
 298                           number that must be unique in cascaded configurations
 299 - #address-cells        : Must be 1
 300 - #size-cells           : Must be 0
 301
 302 A switch child node has the following optional property:
 303
 304 - eeprom-length         : Set to the length of an EEPROM connected to the
 305                           switch. Must be set if the switch can not detect
 306                           the presence and/or size of a connected EEPROM,
 307                           otherwise optional.
 308
 309 A switch may have multiple "port" children nodes
 310
 311 Each port children node must have the following mandatory properties:
 312 - reg                   : Describes the port address in the switch
 313 - label                 : Describes the label associated with this port, special
 314                           labels are "cpu" to indicate a CPU port and "dsa" to
 315                           indicate an uplink/downlink port.
 316
 317 Note that a port labelled "dsa" will imply checking for the uplink phandle
 318 described below.
 319
 320 Optional property:
 321 - link                  : Should be a list of phandles to another switch's DSA port.
 322                           This property is only used when switches are being
 323                           chained/cascaded together. This port is used as outgoing port
 324                           towards the phandle port, which can be more than one hop away.
 325
 326 - phy-handle            : Phandle to a PHY on an external MDIO bus, not the
 327                           switch internal one. See
 328                           Documentation/devicetree/bindings/net/ethernet.txt
 329                           for details.
 330
 331 - phy-mode              : String representing the connection to the designated
 332                           PHY node specified by the 'phy-handle' property. See
 333                           Documentation/devicetree/bindings/net/ethernet.txt
 334                           for details.
 335
 336 - mii-bus               : Should be a phandle to a valid MDIO bus device node.
 337                           This mii-bus will be used in preference to the
 338                           global dsa,mii-bus defined above, for this switch.
 339
 340 Optional subnodes:
 341 - fixed-link            : Fixed-link subnode describing a link to a non-MDIO
 342                           managed entity. See
 343                           Documentation/devicetree/bindings/net/fixed-link.txt
 344                           for details.
 345
 346 Example:
 347
 348         dsa@0 {
 349                 compatible = "marvell,dsa";
 350                 #address-cells = <2>;
 351                 #size-cells = <0>;
 352
 353                 interrupts = <10>;
 354                 dsa,ethernet = <&ethernet0>;
 355                 dsa,mii-bus = <&mii_bus0>;
 356
 357                 switch@0 {
 358                         #address-cells = <1>;
 359                         #size-cells = <0>;
 360                         reg = <16 0>;   /* MDIO address 16, switch 0 in tree */
 361
 362                         port@0 {
 363                                 reg = <0>;
 364                                 label = "lan1";
 365                                 phy-handle = <&phy0>;
 366                         };
 367
 368                         port@1 {
 369                                 reg = <1>;
 370                                 label = "lan2";
 371                         };
 372
 373                         port@5 {
 374                                 reg = <5>;
 375                                 label = "cpu";
 376                         };
 377
 378                         switch0port6: port@6 {
 379                                 reg = <6>;
 380                                 label = "dsa";
 381                                 link = <&switch1port0
 382                                         &switch2port0>;
 383                         };
 384                 };
 385
 386                 switch@1 {
 387                         #address-cells = <1>;
 388                         #size-cells = <0>;
 389                         reg = <17 1>;   /* MDIO address 17, switch 1 in tree */
 390                         mii-bus = <&mii_bus1>;
 391                         reset-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
 392
 393                         switch1port0: port@0 {
 394                                 reg = <0>;
 395                                 label = "dsa";
 396                                 link = <&switch0port6>;
 397                         };
 398                         switch1port1: port@1 {
 399                                 reg = <1>;
 400                                 label = "dsa";
 401                                 link = <&switch2port1>;
 402                         };
 403                 };
 404
 405                 switch@2 {
 406                         #address-cells = <1>;
 407                         #size-cells = <0>;
 408                         reg = <18 2>;   /* MDIO address 18, switch 2 in tree */
 409                         mii-bus = <&mii_bus1>;
 410
 411                         switch2port0: port@0 {
 412                                 reg = <0>;
 413                                 label = "dsa";
 414                                 link = <&switch1port1
 415                                         &switch0port6>;
 416                         };
 417                 };
 418         };