Documentation/devicetree/bindings/mtd/mtk-nand.txt

   1 MTK SoCs NAND FLASH controller (NFC) DT binding
   2
   3 This file documents the device tree bindings for MTK SoCs NAND controllers.
   4 The functional split of the controller requires two drivers to operate:
   5 the nand controller interface driver and the ECC engine driver.
   6
   7 The hardware description for both devices must be captured as device
   8 tree nodes.
   9
  10 1) NFC NAND Controller Interface (NFI):
  11 =======================================
  12
  13 The first part of NFC is NAND Controller Interface (NFI) HW.
  14 Required NFI properties:
  15 - compatible:                   Should be one of
  16                                 "mediatek,mt2701-nfc",
  17                                 "mediatek,mt2712-nfc",
  18                                 "mediatek,mt7622-nfc".
  19 - reg:                          Base physical address and size of NFI.
  20 - interrupts:                   Interrupts of NFI.
  21 - clocks:                       NFI required clocks.
  22 - clock-names:                  NFI clocks internal name.
  23 - status:                       Disabled default. Then set "okay" by platform.
  24 - ecc-engine:                   Required ECC Engine node.
  25 - #address-cells:               NAND chip index, should be 1.
  26 - #size-cells:                  Should be 0.
  27
  28 Example:
  29
  30         nandc: nfi@1100d000 {
  31                 compatible = "mediatek,mt2701-nfc";
  32                 reg = <0 0x1100d000 0 0x1000>;
  33                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
  34                 clocks = <&pericfg CLK_PERI_NFI>,
  35                          <&pericfg CLK_PERI_NFI_PAD>;
  36                 clock-names = "nfi_clk", "pad_clk";
  37                 status = "disabled";
  38                 ecc-engine = <&bch>;
  39                 #address-cells = <1>;
  40                 #size-cells = <0>;
  41         };
  42
  43 Platform related properties, should be set in {platform_name}.dts:
  44 - children nodes:       NAND chips.
  45
  46 Children nodes properties:
  47 - reg:                  Chip Select Signal, default 0.
  48                         Set as reg = <0>, <1> when need 2 CS.
  49 Optional:
  50 - nand-on-flash-bbt:    Store BBT on NAND Flash.
  51 - nand-ecc-mode:        the NAND ecc mode (check driver for supported modes)
  52 - nand-ecc-step-size:   Number of data bytes covered by a single ECC step.
  53                         valid values: 512 and 1024.
  54                         1024 is recommended for large page NANDs.
  55 - nand-ecc-strength:    Number of bits to correct per ECC step.
  56                         The valid values that the controller supports are: 4, 6,
  57                         8, 10, 12, 14, 16, 18, 20, 22, 24, 28, 32, 36, 40, 44,
  58                         48, 52, 56, 60.
  59                         The strength should be calculated as follows:
  60                         E = (S - F) * 8 / 14
  61                         S = O / (P / Q)
  62                                 E :     nand-ecc-strength.
  63                                 S :     spare size per sector.
  64                                 F :     FDM size, should be in the range [1,8].
  65                                         It is used to store free oob data.
  66                                 O :     oob size.
  67                                 P :     page size.
  68                                 Q :     nand-ecc-step-size.
  69                         If the result does not match any one of the listed
  70                         choices above, please select the smaller valid value from
  71                         the list.
  72                         (otherwise the driver will do the adjustment at runtime)
  73 - pinctrl-names:        Default NAND pin GPIO setting name.
  74 - pinctrl-0:            GPIO setting node.
  75
  76 Example:
  77         &pio {
  78                 nand_pins_default: nanddefault {
  79                         pins_dat {
  80                                 pinmux = <MT2701_PIN_111_MSDC0_DAT7__FUNC_NLD7>,
  81                                          <MT2701_PIN_112_MSDC0_DAT6__FUNC_NLD6>,
  82                                          <MT2701_PIN_114_MSDC0_DAT4__FUNC_NLD4>,
  83                                          <MT2701_PIN_118_MSDC0_DAT3__FUNC_NLD3>,
  84                                          <MT2701_PIN_121_MSDC0_DAT0__FUNC_NLD0>,
  85                                          <MT2701_PIN_120_MSDC0_DAT1__FUNC_NLD1>,
  86                                          <MT2701_PIN_113_MSDC0_DAT5__FUNC_NLD5>,
  87                                          <MT2701_PIN_115_MSDC0_RSTB__FUNC_NLD8>,
  88                                          <MT2701_PIN_119_MSDC0_DAT2__FUNC_NLD2>;
  89                                 input-enable;
  90                                 drive-strength = <MTK_DRIVE_8mA>;
  91                                 bias-pull-up;
  92                         };
  93
  94                         pins_we {
  95                                 pinmux = <MT2701_PIN_117_MSDC0_CLK__FUNC_NWEB>;
  96                                 drive-strength = <MTK_DRIVE_8mA>;
  97                                 bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
  98                         };
  99
 100                         pins_ale {
 101                                 pinmux = <MT2701_PIN_116_MSDC0_CMD__FUNC_NALE>;
 102                                 drive-strength = <MTK_DRIVE_8mA>;
 103                                 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
 104                         };
 105                 };
 106         };
 107
 108         &nandc {
 109                 status = "okay";
 110                 pinctrl-names = "default";
 111                 pinctrl-0 = <&nand_pins_default>;
 112                 nand@0 {
 113                         reg = <0>;
 114                         nand-on-flash-bbt;
 115                         nand-ecc-mode = "hw";
 116                         nand-ecc-strength = <24>;
 117                         nand-ecc-step-size = <1024>;
 118                 };
 119         };
 120
 121 NAND chip optional subnodes:
 122 - Partitions, see Documentation/devicetree/bindings/mtd/partition.txt
 123
 124 Example:
 125         nand@0 {
 126                 partitions {
 127                         compatible = "fixed-partitions";
 128                         #address-cells = <1>;
 129                         #size-cells = <1>;
 130
 131                         preloader@0 {
 132                                 label = "pl";
 133                                 read-only;
 134                                 reg = <0x00000000 0x00400000>;
 135                         };
 136                         android@00400000 {
 137                                 label = "android";
 138                                 reg = <0x00400000 0x12c00000>;
 139                         };
 140                 };
 141         };
 142
 143 2) ECC Engine:
 144 ==============
 145
 146 Required BCH properties:
 147 - compatible:   Should be one of
 148                 "mediatek,mt2701-ecc",
 149                 "mediatek,mt2712-ecc",
 150                 "mediatek,mt7622-ecc".
 151 - reg:          Base physical address and size of ECC.
 152 - interrupts:   Interrupts of ECC.
 153 - clocks:       ECC required clocks.
 154 - clock-names:  ECC clocks internal name.
 155 - status:       Disabled default. Then set "okay" by platform.
 156
 157 Example:
 158
 159         bch: ecc@1100e000 {
 160                 compatible = "mediatek,mt2701-ecc";
 161                 reg = <0 0x1100e000 0 0x1000>;
 162                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
 163                 clocks = <&pericfg CLK_PERI_NFI_ECC>;
 164                 clock-names = "nfiecc_clk";
 165                 status = "disabled";
 166         };