3 The MTK MSDC can act as a MMC controller
4 to support MMC, SD, and SDIO types of memory cards.
6 This file documents differences between the core properties in mmc.txt
7 and the properties used by the msdc driver.
10 - compatible: value should be either of the following.
11 "mediatek,mt8135-mmc": for mmc host ip compatible with mt8135
12 "mediatek,mt8173-mmc": for mmc host ip compatible with mt8173
13 "mediatek,mt8183-mmc": for mmc host ip compatible with mt8183
14 "mediatek,mt2701-mmc": for mmc host ip compatible with mt2701
15 "mediatek,mt2712-mmc": for mmc host ip compatible with mt2712
16 "mediatek,mt7622-mmc": for MT7622 SoC
17 "mediatek,mt7623-mmc", "mediatek,mt2701-mmc": for MT7623 SoC
19 - reg: physical base address of the controller and length
20 - interrupts: Should contain MSDC interrupt number
21 - clocks: Should contain phandle for the clock feeding the MMC controller
22 - clock-names: Should contain the following:
23 "source" - source clock (required)
24 "hclk" - HCLK which used for host (required)
25 "source_cg" - independent source clock gate (required for MT2712)
26 "bus_clk" - bus clock used for internal register access (required for MT2712 MSDC0/3)
27 - pinctrl-names: should be "default", "state_uhs"
28 - pinctrl-0: should contain default/high speed pin ctrl
29 - pinctrl-1: should contain uhs mode pin ctrl
30 - vmmc-supply: power to the Core
31 - vqmmc-supply: power to the IO
34 - assigned-clocks: PLL of the source clock
35 - assigned-clock-parents: parent of source clock, used for HS400 mode to get 400Mhz source clock
36 - hs400-ds-delay: HS400 DS delay setting
37 - mediatek,hs200-cmd-int-delay: HS200 command internal delay setting.
38 This field has total 32 stages.
39 The value is an integer from 0 to 31.
40 - mediatek,hs400-cmd-int-delay: HS400 command internal delay setting
41 This field has total 32 stages.
42 The value is an integer from 0 to 31.
43 - mediatek,hs400-cmd-resp-sel-rising: HS400 command response sample selection
44 If present,HS400 command responses are sampled on rising edges.
45 If not present,HS400 command responses are sampled on falling edges.
46 - mediatek,latch-ck: Some SoCs do not support enhance_rx, need set correct latch-ck to avoid data crc
47 error caused by stop clock(fifo full)
48 Valid range = [0:0x7]. if not present, default value is 0.
49 applied to compatible "mediatek,mt2701-mmc".
53 compatible = "mediatek,mt8173-mmc", "mediatek,mt8135-mmc";
54 reg = <0 0x11230000 0 0x108>;
55 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
56 vmmc-supply = <&mt6397_vemc_3v3_reg>;
57 vqmmc-supply = <&mt6397_vio18_reg>;
58 clocks = <&pericfg CLK_PERI_MSDC30_0>,
59 <&topckgen CLK_TOP_MSDC50_0_H_SEL>;
60 clock-names = "source", "hclk";
61 pinctrl-names = "default", "state_uhs";
62 pinctrl-0 = <&mmc0_pins_default>;
63 pinctrl-1 = <&mmc0_pins_uhs>;
64 assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
65 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
66 hs400-ds-delay = <0x14015>;
67 mediatek,hs200-cmd-int-delay = <26>;
68 mediatek,hs400-cmd-int-delay = <14>;
69 mediatek,hs400-cmd-resp-sel-rising;