Documentation/devicetree/bindings/mmc/mtk-sd.txt

   1 * MTK MMC controller
   2
   3 The MTK  MSDC can act as a MMC controller
   4 to support MMC, SD, and SDIO types of memory cards.
   5
   6 This file documents differences between the core properties in mmc.txt
   7 and the properties used by the msdc driver.
   8
   9 Required properties:
  10 - compatible: Should be "mediatek,mt8173-mmc","mediatek,mt8135-mmc"
  11 - interrupts: Should contain MSDC interrupt number
  12 - clocks: MSDC source clock, HCLK
  13 - clock-names: "source", "hclk"
  14 - pinctrl-names: should be "default", "state_uhs"
  15 - pinctrl-0: should contain default/high speed pin ctrl
  16 - pinctrl-1: should contain uhs mode pin ctrl
  17 - vmmc-supply: power to the Core
  18 - vqmmc-supply: power to the IO
  19
  20 Optional properties:
  21 - assigned-clocks: PLL of the source clock
  22 - assigned-clock-parents: parent of source clock, used for HS400 mode to get 400Mhz source clock
  23 - hs400-ds-delay: HS400 DS delay setting
  24 - mediatek,hs200-cmd-int-delay: HS200 command internal delay setting.
  25                                 This field has total 32 stages.
  26                                 The value is an integer from 0 to 31.
  27 - mediatek,hs400-cmd-int-delay: HS400 command internal delay setting
  28                                 This field has total 32 stages.
  29                                 The value is an integer from 0 to 31.
  30 - mediatek,hs400-cmd-resp-sel-rising:  HS400 command response sample selection
  31                                        If present,HS400 command responses are sampled on rising edges.
  32                                        If not present,HS400 command responses are sampled on falling edges.
  33
  34 Examples:
  35 mmc0: mmc@11230000 {
  36         compatible = "mediatek,mt8173-mmc", "mediatek,mt8135-mmc";
  37         reg = <0 0x11230000 0 0x108>;
  38         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
  39         vmmc-supply = <&mt6397_vemc_3v3_reg>;
  40         vqmmc-supply = <&mt6397_vio18_reg>;
  41         clocks = <&pericfg CLK_PERI_MSDC30_0>,
  42                  <&topckgen CLK_TOP_MSDC50_0_H_SEL>;
  43         clock-names = "source", "hclk";
  44         pinctrl-names = "default", "state_uhs";
  45         pinctrl-0 = <&mmc0_pins_default>;
  46         pinctrl-1 = <&mmc0_pins_uhs>;
  47         assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
  48         assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
  49         hs400-ds-delay = <0x14015>;
  50         mediatek,hs200-cmd-int-delay = <26>;
  51         mediatek,hs400-cmd-int-delay = <14>;
  52         mediatek,hs400-cmd-resp-sel-rising;
  53 };