Documentation/devicetree/bindings/media/mediatek-vcodec.txt

   1 Mediatek Video Codec
   2
   3 Mediatek Video Codec is the video codec hw present in Mediatek SoCs which
   4 supports high resolution encoding and decoding functionalities.
   5
   6 Required properties:
   7 - compatible : "mediatek,mt8173-vcodec-enc" for encoder
   8   "mediatek,mt8173-vcodec-dec" for decoder.
   9 - reg : Physical base address of the video codec registers and length of
  10   memory mapped region.
  11 - interrupts : interrupt number to the cpu.
  12 - mediatek,larb : must contain the local arbiters in the current Socs.
  13 - clocks : list of clock specifiers, corresponding to entries in
  14   the clock-names property.
  15 - clock-names: encoder must contain "venc_sel_src", "venc_sel",,
  16   "venc_lt_sel_src", "venc_lt_sel", decoder must contain "vcodecpll",
  17   "univpll_d2", "clk_cci400_sel", "vdec_sel", "vdecpll", "vencpll",
  18   "venc_lt_sel", "vdec_bus_clk_src".
  19 - iommus : should point to the respective IOMMU block with master port as
  20   argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
  21   for details.
  22 - mediatek,vpu : the node of video processor unit
  23
  24
  25 Example:
  26
  27 vcodec_dec: vcodec@16000000 {
  28     compatible = "mediatek,mt8173-vcodec-dec";
  29     reg = <0 0x16000000 0 0x100>,   /*VDEC_SYS*/
  30           <0 0x16020000 0 0x1000>,  /*VDEC_MISC*/
  31           <0 0x16021000 0 0x800>,   /*VDEC_LD*/
  32           <0 0x16021800 0 0x800>,   /*VDEC_TOP*/
  33           <0 0x16022000 0 0x1000>,  /*VDEC_CM*/
  34           <0 0x16023000 0 0x1000>,  /*VDEC_AD*/
  35           <0 0x16024000 0 0x1000>,  /*VDEC_AV*/
  36           <0 0x16025000 0 0x1000>,  /*VDEC_PP*/
  37           <0 0x16026800 0 0x800>,   /*VP8_VD*/
  38           <0 0x16027000 0 0x800>,   /*VP6_VD*/
  39           <0 0x16027800 0 0x800>,   /*VP8_VL*/
  40           <0 0x16028400 0 0x400>;   /*VP9_VD*/
  41     interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>;
  42     mediatek,larb = <&larb1>;
  43     iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>,
  44              <&iommu M4U_PORT_HW_VDEC_PP_EXT>,
  45              <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>,
  46              <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>,
  47              <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>,
  48              <&iommu M4U_PORT_HW_VDEC_UFO_EXT>,
  49              <&iommu M4U_PORT_HW_VDEC_VLD_EXT>,
  50              <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>;
  51     mediatek,vpu = <&vpu>;
  52     power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
  53     clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>,
  54              <&topckgen CLK_TOP_UNIVPLL_D2>,
  55              <&topckgen CLK_TOP_CCI400_SEL>,
  56              <&topckgen CLK_TOP_VDEC_SEL>,
  57              <&topckgen CLK_TOP_VCODECPLL>,
  58              <&apmixedsys CLK_APMIXED_VENCPLL>,
  59              <&topckgen CLK_TOP_VENC_LT_SEL>,
  60              <&topckgen CLK_TOP_VCODECPLL_370P5>;
  61     clock-names = "vcodecpll",
  62                   "univpll_d2",
  63                   "clk_cci400_sel",
  64                   "vdec_sel",
  65                   "vdecpll",
  66                   "vencpll",
  67                   "venc_lt_sel",
  68                   "vdec_bus_clk_src";
  69     assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>,
  70                       <&topckgen CLK_TOP_CCI400_SEL>,
  71                       <&topckgen CLK_TOP_VDEC_SEL>,
  72                       <&apmixedsys CLK_APMIXED_VCODECPLL>,
  73                       <&apmixedsys CLK_APMIXED_VENCPLL>;
  74     assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>,
  75                              <&topckgen CLK_TOP_UNIVPLL_D2>,
  76                              <&topckgen CLK_TOP_VCODECPLL>;
  77     assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>;
  78   };
  79
  80   vcodec_enc: vcodec@18002000 {
  81     compatible = "mediatek,mt8173-vcodec-enc";
  82     reg = <0 0x18002000 0 0x1000>,    /*VENC_SYS*/
  83           <0 0x19002000 0 0x1000>;    /*VENC_LT_SYS*/
  84     interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>,
  85                  <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>;
  86     mediatek,larb = <&larb3>,
  87                     <&larb5>;
  88     iommus = <&iommu M4U_PORT_VENC_RCPU>,
  89              <&iommu M4U_PORT_VENC_REC>,
  90              <&iommu M4U_PORT_VENC_BSDMA>,
  91              <&iommu M4U_PORT_VENC_SV_COMV>,
  92              <&iommu M4U_PORT_VENC_RD_COMV>,
  93              <&iommu M4U_PORT_VENC_CUR_LUMA>,
  94              <&iommu M4U_PORT_VENC_CUR_CHROMA>,
  95              <&iommu M4U_PORT_VENC_REF_LUMA>,
  96              <&iommu M4U_PORT_VENC_REF_CHROMA>,
  97              <&iommu M4U_PORT_VENC_NBM_RDMA>,
  98              <&iommu M4U_PORT_VENC_NBM_WDMA>,
  99              <&iommu M4U_PORT_VENC_RCPU_SET2>,
 100              <&iommu M4U_PORT_VENC_REC_FRM_SET2>,
 101              <&iommu M4U_PORT_VENC_BSDMA_SET2>,
 102              <&iommu M4U_PORT_VENC_SV_COMA_SET2>,
 103              <&iommu M4U_PORT_VENC_RD_COMA_SET2>,
 104              <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>,
 105              <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>,
 106              <&iommu M4U_PORT_VENC_REF_LUMA_SET2>,
 107              <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>;
 108     mediatek,vpu = <&vpu>;
 109     clocks = <&topckgen CLK_TOP_VENCPLL_D2>,
 110              <&topckgen CLK_TOP_VENC_SEL>,
 111              <&topckgen CLK_TOP_UNIVPLL1_D2>,
 112              <&topckgen CLK_TOP_VENC_LT_SEL>;
 113     clock-names = "venc_sel_src",
 114                   "venc_sel",
 115                   "venc_lt_sel_src",
 116                   "venc_lt_sel";
 117     assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>,
 118                       <&topckgen CLK_TOP_VENC_LT_SEL>;
 119     assigned-clock-parents = <&topckgen CLK_TOP_VENCPLL_D2>,
 120                              <&topckgen CLK_TOP_UNIVPLL1_D2>;
 121   };