Documentation/devicetree/bindings/media/mediatek-mdp.txt

   1 * Mediatek Media Data Path
   2
   3 Media Data Path is used for scaling and color space conversion.
   4
   5 Required properties (controller (parent) node):
   6 - compatible: "mediatek,mt8173-mdp"
   7 - mediatek,vpu: the node of video processor unit, see
   8   Documentation/devicetree/bindings/media/mediatek-vpu.txt for details.
   9
  10 Required properties (all function blocks, child node):
  11 - compatible: Should be one of
  12         "mediatek,mt8173-mdp-rdma"  - read DMA
  13         "mediatek,mt8173-mdp-rsz"   - resizer
  14         "mediatek,mt8173-mdp-wdma"  - write DMA
  15         "mediatek,mt8173-mdp-wrot"  - write DMA with rotation
  16 - reg: Physical base address and length of the function block register space
  17 - clocks: device clocks, see
  18   Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
  19 - power-domains: a phandle to the power domain, see
  20   Documentation/devicetree/bindings/power/power_domain.txt for details.
  21
  22 Required properties (DMA function blocks, child node):
  23 - compatible: Should be one of
  24         "mediatek,mt8173-mdp-rdma"
  25         "mediatek,mt8173-mdp-wdma"
  26         "mediatek,mt8173-mdp-wrot"
  27 - iommus: should point to the respective IOMMU block with master port as
  28   argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
  29   for details.
  30 - mediatek,larb: must contain the local arbiters in the current Socs, see
  31   Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
  32   for details.
  33
  34 Example:
  35 mdp {
  36         compatible = "mediatek,mt8173-mdp";
  37         #address-cells = <2>;
  38         #size-cells = <2>;
  39         ranges;
  40         mediatek,vpu = <&vpu>;
  41
  42         mdp_rdma0: rdma@14001000 {
  43                 compatible = "mediatek,mt8173-mdp-rdma";
  44                 reg = <0 0x14001000 0 0x1000>;
  45                 clocks = <&mmsys CLK_MM_MDP_RDMA0>,
  46                          <&mmsys CLK_MM_MUTEX_32K>;
  47                 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
  48                 iommus = <&iommu M4U_PORT_MDP_RDMA0>;
  49                 mediatek,larb = <&larb0>;
  50         };
  51
  52         mdp_rdma1: rdma@14002000 {
  53                 compatible = "mediatek,mt8173-mdp-rdma";
  54                 reg = <0 0x14002000 0 0x1000>;
  55                 clocks = <&mmsys CLK_MM_MDP_RDMA1>,
  56                          <&mmsys CLK_MM_MUTEX_32K>;
  57                 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
  58                 iommus = <&iommu M4U_PORT_MDP_RDMA1>;
  59                 mediatek,larb = <&larb4>;
  60         };
  61
  62         mdp_rsz0: rsz@14003000 {
  63                 compatible = "mediatek,mt8173-mdp-rsz";
  64                 reg = <0 0x14003000 0 0x1000>;
  65                 clocks = <&mmsys CLK_MM_MDP_RSZ0>;
  66                 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
  67         };
  68
  69         mdp_rsz1: rsz@14004000 {
  70                 compatible = "mediatek,mt8173-mdp-rsz";
  71                 reg = <0 0x14004000 0 0x1000>;
  72                 clocks = <&mmsys CLK_MM_MDP_RSZ1>;
  73                 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
  74         };
  75
  76         mdp_rsz2: rsz@14005000 {
  77                 compatible = "mediatek,mt8173-mdp-rsz";
  78                 reg = <0 0x14005000 0 0x1000>;
  79                 clocks = <&mmsys CLK_MM_MDP_RSZ2>;
  80                 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
  81         };
  82
  83         mdp_wdma0: wdma@14006000 {
  84                 compatible = "mediatek,mt8173-mdp-wdma";
  85                 reg = <0 0x14006000 0 0x1000>;
  86                 clocks = <&mmsys CLK_MM_MDP_WDMA>;
  87                 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
  88                 iommus = <&iommu M4U_PORT_MDP_WDMA>;
  89                 mediatek,larb = <&larb0>;
  90         };
  91
  92         mdp_wrot0: wrot@14007000 {
  93                 compatible = "mediatek,mt8173-mdp-wrot";
  94                 reg = <0 0x14007000 0 0x1000>;
  95                 clocks = <&mmsys CLK_MM_MDP_WROT0>;
  96                 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
  97                 iommus = <&iommu M4U_PORT_MDP_WROT0>;
  98                 mediatek,larb = <&larb0>;
  99         };
 100
 101         mdp_wrot1: wrot@14008000 {
 102                 compatible = "mediatek,mt8173-mdp-wrot";
 103                 reg = <0 0x14008000 0 0x1000>;
 104                 clocks = <&mmsys CLK_MM_MDP_WROT1>;
 105                 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
 106                 iommus = <&iommu M4U_PORT_MDP_WROT1>;
 107                 mediatek,larb = <&larb4>;
 108         };
 109 };