Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs
[sfrench/cifs-2.6.git] / Documentation / devicetree / bindings / media / cedrus.txt
1 Device-tree bindings for the VPU found in Allwinner SoCs, referred to as the
2 Video Engine (VE) in Allwinner literature.
3
4 The VPU can only access the first 256 MiB of DRAM, that are DMA-mapped starting
5 from the DRAM base. This requires specific memory allocation and handling.
6
7 Required properties:
8 - compatible            : must be one of the following compatibles:
9                         - "allwinner,sun4i-a10-video-engine"
10                         - "allwinner,sun5i-a13-video-engine"
11                         - "allwinner,sun7i-a20-video-engine"
12                         - "allwinner,sun8i-a33-video-engine"
13                         - "allwinner,sun8i-h3-video-engine"
14                         - "allwinner,sun50i-a64-video-engine"
15                         - "allwinner,sun50i-h5-video-engine"
16 - reg                   : register base and length of VE;
17 - clocks                : list of clock specifiers, corresponding to entries in
18                           the clock-names property;
19 - clock-names           : should contain "ahb", "mod" and "ram" entries;
20 - resets                : phandle for reset;
21 - interrupts            : VE interrupt number;
22 - allwinner,sram        : SRAM region to use with the VE.
23
24 Optional properties:
25 - memory-region         : CMA pool to use for buffers allocation instead of the
26                           default CMA pool.
27
28 Example:
29
30 reserved-memory {
31         #address-cells = <1>;
32         #size-cells = <1>;
33         ranges;
34
35         /* Address must be kept in the lower 256 MiBs of DRAM for VE. */
36         cma_pool: default-pool {
37                 compatible = "shared-dma-pool";
38                 size = <0x6000000>;
39                 alloc-ranges = <0x4a000000 0x6000000>;
40                 reusable;
41                 linux,cma-default;
42         };
43 };
44
45 video-codec@1c0e000 {
46         compatible = "allwinner,sun7i-a20-video-engine";
47         reg = <0x01c0e000 0x1000>;
48
49         clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>,
50                  <&ccu CLK_DRAM_VE>;
51         clock-names = "ahb", "mod", "ram";
52
53         resets = <&ccu RST_VE>;
54         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
55         allwinner,sram = <&ve_sram 1>;
56 };